Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9064057 |
1 |
|
|
T1 |
1276 |
|
T11 |
421 |
|
T12 |
26760 |
| auto[1] |
7186072 |
1 |
|
|
T1 |
1134 |
|
T12 |
24363 |
|
T13 |
249279 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15324361 |
1 |
|
|
T1 |
2357 |
|
T11 |
421 |
|
T12 |
47758 |
| auto[1] |
925768 |
1 |
|
|
T1 |
53 |
|
T12 |
3365 |
|
T13 |
32238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9055272 |
1 |
|
|
T1 |
1204 |
|
T11 |
421 |
|
T12 |
27608 |
| auto[1] |
7194857 |
1 |
|
|
T1 |
1206 |
|
T12 |
23515 |
|
T13 |
245391 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3153947 |
1 |
|
|
T1 |
556 |
|
T12 |
9438 |
|
T13 |
103314 |
| auto[1] |
auto[0] |
auto[1] |
466450 |
1 |
|
|
T1 |
30 |
|
T12 |
1545 |
|
T13 |
15538 |
| auto[1] |
auto[1] |
auto[0] |
3115142 |
1 |
|
|
T1 |
597 |
|
T12 |
10712 |
|
T13 |
109839 |
| auto[1] |
auto[1] |
auto[1] |
459318 |
1 |
|
|
T1 |
23 |
|
T12 |
1820 |
|
T13 |
16700 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |