Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9078865 |
1 |
|
|
T1 |
1127 |
|
T11 |
421 |
|
T12 |
28015 |
| auto[1] |
7171264 |
1 |
|
|
T1 |
1283 |
|
T12 |
23108 |
|
T13 |
240121 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15320678 |
1 |
|
|
T1 |
2363 |
|
T11 |
421 |
|
T12 |
47809 |
| auto[1] |
929451 |
1 |
|
|
T1 |
47 |
|
T12 |
3314 |
|
T13 |
31825 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9036893 |
1 |
|
|
T1 |
1130 |
|
T11 |
421 |
|
T12 |
27661 |
| auto[1] |
7213236 |
1 |
|
|
T1 |
1280 |
|
T12 |
23462 |
|
T13 |
242090 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3170001 |
1 |
|
|
T1 |
595 |
|
T12 |
9987 |
|
T13 |
106069 |
| auto[1] |
auto[0] |
auto[1] |
470231 |
1 |
|
|
T1 |
25 |
|
T12 |
1649 |
|
T13 |
16218 |
| auto[1] |
auto[1] |
auto[0] |
3113784 |
1 |
|
|
T1 |
638 |
|
T12 |
10161 |
|
T13 |
104196 |
| auto[1] |
auto[1] |
auto[1] |
459220 |
1 |
|
|
T1 |
22 |
|
T12 |
1665 |
|
T13 |
15607 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |