Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9019766 |
1 |
|
|
T1 |
1245 |
|
T11 |
421 |
|
T12 |
27180 |
| auto[1] |
7230363 |
1 |
|
|
T1 |
1165 |
|
T12 |
23943 |
|
T13 |
238605 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13351623 |
1 |
|
|
T1 |
2102 |
|
T11 |
421 |
|
T12 |
41055 |
| auto[1] |
2898506 |
1 |
|
|
T1 |
308 |
|
T12 |
10068 |
|
T13 |
89918 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9053888 |
1 |
|
|
T1 |
1110 |
|
T11 |
421 |
|
T12 |
27492 |
| auto[1] |
7196241 |
1 |
|
|
T1 |
1300 |
|
T12 |
23631 |
|
T13 |
231168 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2133770 |
1 |
|
|
T1 |
508 |
|
T12 |
6497 |
|
T13 |
70174 |
| auto[1] |
auto[0] |
auto[1] |
1445980 |
1 |
|
|
T1 |
138 |
|
T12 |
4989 |
|
T13 |
45321 |
| auto[1] |
auto[1] |
auto[0] |
2163965 |
1 |
|
|
T1 |
484 |
|
T12 |
7066 |
|
T13 |
71076 |
| auto[1] |
auto[1] |
auto[1] |
1452526 |
1 |
|
|
T1 |
170 |
|
T12 |
5079 |
|
T13 |
44597 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |