Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9062565 |
1 |
|
|
T1 |
1084 |
|
T11 |
421 |
|
T12 |
28180 |
| auto[1] |
7187564 |
1 |
|
|
T1 |
1326 |
|
T12 |
22943 |
|
T13 |
240874 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13342290 |
1 |
|
|
T1 |
2216 |
|
T11 |
421 |
|
T12 |
41104 |
| auto[1] |
2907839 |
1 |
|
|
T1 |
194 |
|
T12 |
10019 |
|
T13 |
90081 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9044332 |
1 |
|
|
T1 |
1335 |
|
T11 |
421 |
|
T12 |
27637 |
| auto[1] |
7205797 |
1 |
|
|
T1 |
1075 |
|
T12 |
23486 |
|
T13 |
234949 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2156474 |
1 |
|
|
T1 |
392 |
|
T12 |
6904 |
|
T13 |
73491 |
| auto[1] |
auto[0] |
auto[1] |
1457917 |
1 |
|
|
T1 |
82 |
|
T12 |
5030 |
|
T13 |
45259 |
| auto[1] |
auto[1] |
auto[0] |
2141484 |
1 |
|
|
T1 |
489 |
|
T12 |
6563 |
|
T13 |
71377 |
| auto[1] |
auto[1] |
auto[1] |
1449922 |
1 |
|
|
T1 |
112 |
|
T12 |
4989 |
|
T13 |
44822 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |