Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9094555 |
1 |
|
|
T1 |
1025 |
|
T11 |
421 |
|
T12 |
27689 |
| auto[1] |
7155574 |
1 |
|
|
T1 |
1385 |
|
T12 |
23434 |
|
T13 |
236275 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13358972 |
1 |
|
|
T1 |
2148 |
|
T11 |
421 |
|
T12 |
41224 |
| auto[1] |
2891157 |
1 |
|
|
T1 |
262 |
|
T12 |
9899 |
|
T13 |
90292 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9067239 |
1 |
|
|
T1 |
1345 |
|
T11 |
421 |
|
T12 |
27839 |
| auto[1] |
7182890 |
1 |
|
|
T1 |
1065 |
|
T12 |
23284 |
|
T13 |
238709 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2163847 |
1 |
|
|
T1 |
310 |
|
T12 |
6534 |
|
T13 |
76528 |
| auto[1] |
auto[0] |
auto[1] |
1456645 |
1 |
|
|
T1 |
142 |
|
T12 |
4683 |
|
T13 |
45437 |
| auto[1] |
auto[1] |
auto[0] |
2127886 |
1 |
|
|
T1 |
493 |
|
T12 |
6851 |
|
T13 |
71889 |
| auto[1] |
auto[1] |
auto[1] |
1434512 |
1 |
|
|
T1 |
120 |
|
T12 |
5216 |
|
T13 |
44855 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |