Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9054248 |
1 |
|
|
T1 |
956 |
|
T11 |
421 |
|
T12 |
28962 |
| auto[1] |
7195881 |
1 |
|
|
T1 |
1454 |
|
T12 |
22161 |
|
T13 |
238390 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13337801 |
1 |
|
|
T1 |
2210 |
|
T11 |
421 |
|
T12 |
41363 |
| auto[1] |
2912328 |
1 |
|
|
T1 |
200 |
|
T12 |
9760 |
|
T13 |
92554 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9026233 |
1 |
|
|
T1 |
1304 |
|
T11 |
421 |
|
T12 |
27373 |
| auto[1] |
7223896 |
1 |
|
|
T1 |
1106 |
|
T12 |
23750 |
|
T13 |
240953 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2163972 |
1 |
|
|
T1 |
433 |
|
T12 |
7125 |
|
T13 |
71176 |
| auto[1] |
auto[0] |
auto[1] |
1460499 |
1 |
|
|
T1 |
82 |
|
T12 |
4989 |
|
T13 |
45402 |
| auto[1] |
auto[1] |
auto[0] |
2147596 |
1 |
|
|
T1 |
473 |
|
T12 |
6865 |
|
T13 |
77223 |
| auto[1] |
auto[1] |
auto[1] |
1451829 |
1 |
|
|
T1 |
118 |
|
T12 |
4771 |
|
T13 |
47152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |