Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9047594 |
1 |
|
|
T1 |
1174 |
|
T11 |
421 |
|
T12 |
27802 |
| auto[1] |
7202535 |
1 |
|
|
T1 |
1236 |
|
T12 |
23321 |
|
T13 |
246908 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13343319 |
1 |
|
|
T1 |
2124 |
|
T11 |
421 |
|
T12 |
41301 |
| auto[1] |
2906810 |
1 |
|
|
T1 |
286 |
|
T12 |
9822 |
|
T13 |
90396 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9037502 |
1 |
|
|
T1 |
1157 |
|
T11 |
421 |
|
T12 |
27200 |
| auto[1] |
7212627 |
1 |
|
|
T1 |
1253 |
|
T12 |
23923 |
|
T13 |
236822 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2159543 |
1 |
|
|
T1 |
458 |
|
T12 |
7247 |
|
T13 |
70602 |
| auto[1] |
auto[0] |
auto[1] |
1455846 |
1 |
|
|
T1 |
157 |
|
T12 |
4952 |
|
T13 |
44353 |
| auto[1] |
auto[1] |
auto[0] |
2146274 |
1 |
|
|
T1 |
509 |
|
T12 |
6854 |
|
T13 |
75824 |
| auto[1] |
auto[1] |
auto[1] |
1450964 |
1 |
|
|
T1 |
129 |
|
T12 |
4870 |
|
T13 |
46043 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |