Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9035899 |
1 |
|
|
T1 |
1393 |
|
T11 |
421 |
|
T12 |
28311 |
| auto[1] |
7214230 |
1 |
|
|
T1 |
1017 |
|
T12 |
22812 |
|
T13 |
246141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15320959 |
1 |
|
|
T1 |
2374 |
|
T11 |
421 |
|
T12 |
48018 |
| auto[1] |
929170 |
1 |
|
|
T1 |
36 |
|
T12 |
3105 |
|
T13 |
31076 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9022520 |
1 |
|
|
T1 |
1372 |
|
T11 |
421 |
|
T12 |
28873 |
| auto[1] |
7227609 |
1 |
|
|
T1 |
1038 |
|
T12 |
22250 |
|
T13 |
239711 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3152430 |
1 |
|
|
T1 |
480 |
|
T12 |
9841 |
|
T13 |
103765 |
| auto[1] |
auto[0] |
auto[1] |
464641 |
1 |
|
|
T1 |
20 |
|
T12 |
1585 |
|
T13 |
15407 |
| auto[1] |
auto[1] |
auto[0] |
3146009 |
1 |
|
|
T1 |
522 |
|
T12 |
9304 |
|
T13 |
104870 |
| auto[1] |
auto[1] |
auto[1] |
464529 |
1 |
|
|
T1 |
16 |
|
T12 |
1520 |
|
T13 |
15669 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |