Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9074162 |
1 |
|
|
T1 |
1405 |
|
T11 |
421 |
|
T12 |
27717 |
| auto[1] |
7175967 |
1 |
|
|
T1 |
1005 |
|
T12 |
23406 |
|
T13 |
250536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13349770 |
1 |
|
|
T1 |
2136 |
|
T11 |
421 |
|
T12 |
41302 |
| auto[1] |
2900359 |
1 |
|
|
T1 |
274 |
|
T12 |
9821 |
|
T13 |
92444 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9038142 |
1 |
|
|
T1 |
1247 |
|
T11 |
421 |
|
T12 |
28103 |
| auto[1] |
7211987 |
1 |
|
|
T1 |
1163 |
|
T12 |
23020 |
|
T13 |
241736 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2176850 |
1 |
|
|
T1 |
537 |
|
T12 |
6715 |
|
T13 |
74320 |
| auto[1] |
auto[0] |
auto[1] |
1460943 |
1 |
|
|
T1 |
149 |
|
T12 |
4892 |
|
T13 |
46000 |
| auto[1] |
auto[1] |
auto[0] |
2134778 |
1 |
|
|
T1 |
352 |
|
T12 |
6484 |
|
T13 |
74972 |
| auto[1] |
auto[1] |
auto[1] |
1439416 |
1 |
|
|
T1 |
125 |
|
T12 |
4929 |
|
T13 |
46444 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |