Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077943 |
1 |
|
|
T1 |
1187 |
|
T11 |
421 |
|
T12 |
28371 |
| auto[1] |
7172186 |
1 |
|
|
T1 |
1223 |
|
T12 |
22752 |
|
T13 |
233224 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13357404 |
1 |
|
|
T1 |
2152 |
|
T11 |
421 |
|
T12 |
41377 |
| auto[1] |
2892725 |
1 |
|
|
T1 |
258 |
|
T12 |
9746 |
|
T13 |
91015 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9074121 |
1 |
|
|
T1 |
1236 |
|
T11 |
421 |
|
T12 |
27861 |
| auto[1] |
7176008 |
1 |
|
|
T1 |
1174 |
|
T12 |
23262 |
|
T13 |
240596 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2155637 |
1 |
|
|
T1 |
426 |
|
T12 |
6629 |
|
T13 |
76782 |
| auto[1] |
auto[0] |
auto[1] |
1455900 |
1 |
|
|
T1 |
144 |
|
T12 |
4923 |
|
T13 |
46120 |
| auto[1] |
auto[1] |
auto[0] |
2127646 |
1 |
|
|
T1 |
490 |
|
T12 |
6887 |
|
T13 |
72799 |
| auto[1] |
auto[1] |
auto[1] |
1436825 |
1 |
|
|
T1 |
114 |
|
T12 |
4823 |
|
T13 |
44895 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |