Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9024640 |
1 |
|
|
T1 |
1141 |
|
T11 |
421 |
|
T12 |
27432 |
| auto[1] |
7225489 |
1 |
|
|
T1 |
1269 |
|
T12 |
23691 |
|
T13 |
240442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13344350 |
1 |
|
|
T1 |
2159 |
|
T11 |
421 |
|
T12 |
41668 |
| auto[1] |
2905779 |
1 |
|
|
T1 |
251 |
|
T12 |
9455 |
|
T13 |
92793 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9041553 |
1 |
|
|
T1 |
1082 |
|
T11 |
421 |
|
T12 |
28187 |
| auto[1] |
7208576 |
1 |
|
|
T1 |
1328 |
|
T12 |
22936 |
|
T13 |
243577 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2148610 |
1 |
|
|
T1 |
544 |
|
T12 |
6770 |
|
T13 |
74463 |
| auto[1] |
auto[0] |
auto[1] |
1455729 |
1 |
|
|
T1 |
130 |
|
T12 |
4819 |
|
T13 |
46083 |
| auto[1] |
auto[1] |
auto[0] |
2154187 |
1 |
|
|
T1 |
533 |
|
T12 |
6711 |
|
T13 |
76321 |
| auto[1] |
auto[1] |
auto[1] |
1450050 |
1 |
|
|
T1 |
121 |
|
T12 |
4636 |
|
T13 |
46710 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |