Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9054463 |
1 |
|
|
T1 |
1172 |
|
T11 |
421 |
|
T12 |
28767 |
| auto[1] |
7195666 |
1 |
|
|
T1 |
1238 |
|
T12 |
22356 |
|
T13 |
232728 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13342880 |
1 |
|
|
T1 |
2093 |
|
T11 |
421 |
|
T12 |
41403 |
| auto[1] |
2907249 |
1 |
|
|
T1 |
317 |
|
T12 |
9720 |
|
T13 |
93708 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9023981 |
1 |
|
|
T1 |
993 |
|
T11 |
421 |
|
T12 |
28863 |
| auto[1] |
7226148 |
1 |
|
|
T1 |
1417 |
|
T12 |
22260 |
|
T13 |
248489 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2175266 |
1 |
|
|
T1 |
518 |
|
T12 |
6426 |
|
T13 |
82327 |
| auto[1] |
auto[0] |
auto[1] |
1458359 |
1 |
|
|
T1 |
149 |
|
T12 |
4594 |
|
T13 |
49116 |
| auto[1] |
auto[1] |
auto[0] |
2143633 |
1 |
|
|
T1 |
582 |
|
T12 |
6114 |
|
T13 |
72454 |
| auto[1] |
auto[1] |
auto[1] |
1448890 |
1 |
|
|
T1 |
168 |
|
T12 |
5126 |
|
T13 |
44592 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |