Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9057419 |
1 |
|
|
T1 |
1198 |
|
T11 |
421 |
|
T12 |
29355 |
| auto[1] |
7192710 |
1 |
|
|
T1 |
1212 |
|
T12 |
21768 |
|
T13 |
245586 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13362540 |
1 |
|
|
T1 |
2148 |
|
T11 |
421 |
|
T12 |
41697 |
| auto[1] |
2887589 |
1 |
|
|
T1 |
262 |
|
T12 |
9426 |
|
T13 |
89764 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9075972 |
1 |
|
|
T1 |
1119 |
|
T11 |
421 |
|
T12 |
28536 |
| auto[1] |
7174157 |
1 |
|
|
T1 |
1291 |
|
T12 |
22587 |
|
T13 |
235291 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2143559 |
1 |
|
|
T1 |
545 |
|
T12 |
7095 |
|
T13 |
69747 |
| auto[1] |
auto[0] |
auto[1] |
1443896 |
1 |
|
|
T1 |
166 |
|
T12 |
4939 |
|
T13 |
43155 |
| auto[1] |
auto[1] |
auto[0] |
2143009 |
1 |
|
|
T1 |
484 |
|
T12 |
6066 |
|
T13 |
75780 |
| auto[1] |
auto[1] |
auto[1] |
1443693 |
1 |
|
|
T1 |
96 |
|
T12 |
4487 |
|
T13 |
46609 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |