Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9036910 |
1 |
|
|
T1 |
1250 |
|
T11 |
421 |
|
T12 |
29035 |
| auto[1] |
7213219 |
1 |
|
|
T1 |
1160 |
|
T12 |
22088 |
|
T13 |
239499 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13358969 |
1 |
|
|
T1 |
2153 |
|
T11 |
421 |
|
T12 |
41314 |
| auto[1] |
2891160 |
1 |
|
|
T1 |
257 |
|
T12 |
9809 |
|
T13 |
93781 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9065974 |
1 |
|
|
T1 |
1083 |
|
T11 |
421 |
|
T12 |
27917 |
| auto[1] |
7184155 |
1 |
|
|
T1 |
1327 |
|
T12 |
23206 |
|
T13 |
244553 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2152615 |
1 |
|
|
T1 |
548 |
|
T12 |
6779 |
|
T13 |
77978 |
| auto[1] |
auto[0] |
auto[1] |
1447707 |
1 |
|
|
T1 |
154 |
|
T12 |
5000 |
|
T13 |
47476 |
| auto[1] |
auto[1] |
auto[0] |
2140380 |
1 |
|
|
T1 |
522 |
|
T12 |
6618 |
|
T13 |
72794 |
| auto[1] |
auto[1] |
auto[1] |
1443453 |
1 |
|
|
T1 |
103 |
|
T12 |
4809 |
|
T13 |
46305 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |