Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9048422 |
1 |
|
|
T1 |
1090 |
|
T11 |
421 |
|
T12 |
27932 |
| auto[1] |
7201707 |
1 |
|
|
T1 |
1320 |
|
T12 |
23191 |
|
T13 |
242302 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13350046 |
1 |
|
|
T1 |
2084 |
|
T11 |
421 |
|
T12 |
41363 |
| auto[1] |
2900083 |
1 |
|
|
T1 |
326 |
|
T12 |
9760 |
|
T13 |
91523 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9060404 |
1 |
|
|
T1 |
1187 |
|
T11 |
421 |
|
T12 |
28023 |
| auto[1] |
7189725 |
1 |
|
|
T1 |
1223 |
|
T12 |
23100 |
|
T13 |
240475 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2147496 |
1 |
|
|
T1 |
402 |
|
T12 |
6976 |
|
T13 |
76952 |
| auto[1] |
auto[0] |
auto[1] |
1451510 |
1 |
|
|
T1 |
134 |
|
T12 |
5005 |
|
T13 |
47205 |
| auto[1] |
auto[1] |
auto[0] |
2142146 |
1 |
|
|
T1 |
495 |
|
T12 |
6364 |
|
T13 |
72000 |
| auto[1] |
auto[1] |
auto[1] |
1448573 |
1 |
|
|
T1 |
192 |
|
T12 |
4755 |
|
T13 |
44318 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |