Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9112368 |
1 |
|
|
T1 |
1323 |
|
T11 |
421 |
|
T12 |
29494 |
| auto[1] |
7137761 |
1 |
|
|
T1 |
1087 |
|
T12 |
21629 |
|
T13 |
242333 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13362859 |
1 |
|
|
T1 |
2072 |
|
T11 |
421 |
|
T12 |
41363 |
| auto[1] |
2887270 |
1 |
|
|
T1 |
338 |
|
T12 |
9760 |
|
T13 |
91367 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9079388 |
1 |
|
|
T1 |
1192 |
|
T11 |
421 |
|
T12 |
28049 |
| auto[1] |
7170741 |
1 |
|
|
T1 |
1218 |
|
T12 |
23074 |
|
T13 |
239148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2160962 |
1 |
|
|
T1 |
527 |
|
T12 |
6977 |
|
T13 |
73707 |
| auto[1] |
auto[0] |
auto[1] |
1451414 |
1 |
|
|
T1 |
168 |
|
T12 |
5261 |
|
T13 |
45897 |
| auto[1] |
auto[1] |
auto[0] |
2122509 |
1 |
|
|
T1 |
353 |
|
T12 |
6337 |
|
T13 |
74074 |
| auto[1] |
auto[1] |
auto[1] |
1435856 |
1 |
|
|
T1 |
170 |
|
T12 |
4499 |
|
T13 |
45470 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |