Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9033331 |
1 |
|
|
T1 |
1217 |
|
T11 |
421 |
|
T12 |
29820 |
| auto[1] |
7216798 |
1 |
|
|
T1 |
1193 |
|
T12 |
21303 |
|
T13 |
243175 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13359598 |
1 |
|
|
T1 |
2160 |
|
T11 |
421 |
|
T12 |
41562 |
| auto[1] |
2890531 |
1 |
|
|
T1 |
250 |
|
T12 |
9561 |
|
T13 |
90654 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9071720 |
1 |
|
|
T1 |
1422 |
|
T11 |
421 |
|
T12 |
28005 |
| auto[1] |
7178409 |
1 |
|
|
T1 |
988 |
|
T12 |
23118 |
|
T13 |
238779 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2137184 |
1 |
|
|
T1 |
399 |
|
T12 |
7464 |
|
T13 |
73043 |
| auto[1] |
auto[0] |
auto[1] |
1440605 |
1 |
|
|
T1 |
85 |
|
T12 |
5187 |
|
T13 |
44682 |
| auto[1] |
auto[1] |
auto[0] |
2150694 |
1 |
|
|
T1 |
339 |
|
T12 |
6093 |
|
T13 |
75082 |
| auto[1] |
auto[1] |
auto[1] |
1449926 |
1 |
|
|
T1 |
165 |
|
T12 |
4374 |
|
T13 |
45972 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |