Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9034551 |
1 |
|
|
T1 |
1305 |
|
T11 |
421 |
|
T12 |
27878 |
| auto[1] |
7215578 |
1 |
|
|
T1 |
1105 |
|
T12 |
23245 |
|
T13 |
246063 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13362337 |
1 |
|
|
T1 |
2134 |
|
T11 |
421 |
|
T12 |
41514 |
| auto[1] |
2887792 |
1 |
|
|
T1 |
276 |
|
T12 |
9609 |
|
T13 |
90842 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9072938 |
1 |
|
|
T1 |
1240 |
|
T11 |
421 |
|
T12 |
28014 |
| auto[1] |
7177191 |
1 |
|
|
T1 |
1170 |
|
T12 |
23109 |
|
T13 |
237627 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2150907 |
1 |
|
|
T1 |
514 |
|
T12 |
6814 |
|
T13 |
72172 |
| auto[1] |
auto[0] |
auto[1] |
1446285 |
1 |
|
|
T1 |
138 |
|
T12 |
4846 |
|
T13 |
44852 |
| auto[1] |
auto[1] |
auto[0] |
2138492 |
1 |
|
|
T1 |
380 |
|
T12 |
6686 |
|
T13 |
74613 |
| auto[1] |
auto[1] |
auto[1] |
1441507 |
1 |
|
|
T1 |
138 |
|
T12 |
4763 |
|
T13 |
45990 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |