Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9056553 |
1 |
|
|
T1 |
1161 |
|
T11 |
421 |
|
T12 |
29117 |
| auto[1] |
7193576 |
1 |
|
|
T1 |
1249 |
|
T12 |
22006 |
|
T13 |
243034 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15327430 |
1 |
|
|
T1 |
2360 |
|
T11 |
421 |
|
T12 |
47644 |
| auto[1] |
922699 |
1 |
|
|
T1 |
50 |
|
T12 |
3479 |
|
T13 |
31455 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9059951 |
1 |
|
|
T1 |
1277 |
|
T11 |
421 |
|
T12 |
26655 |
| auto[1] |
7190178 |
1 |
|
|
T1 |
1133 |
|
T12 |
24468 |
|
T13 |
242467 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3135948 |
1 |
|
|
T1 |
513 |
|
T12 |
11286 |
|
T13 |
103188 |
| auto[1] |
auto[0] |
auto[1] |
461494 |
1 |
|
|
T1 |
18 |
|
T12 |
1875 |
|
T13 |
15264 |
| auto[1] |
auto[1] |
auto[0] |
3131531 |
1 |
|
|
T1 |
570 |
|
T12 |
9703 |
|
T13 |
107824 |
| auto[1] |
auto[1] |
auto[1] |
461205 |
1 |
|
|
T1 |
32 |
|
T12 |
1604 |
|
T13 |
16191 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |