Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9054982 |
1 |
|
|
T1 |
1223 |
|
T11 |
421 |
|
T12 |
27029 |
| auto[1] |
7195147 |
1 |
|
|
T1 |
1187 |
|
T12 |
24094 |
|
T13 |
241014 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13355658 |
1 |
|
|
T1 |
2163 |
|
T11 |
421 |
|
T12 |
41227 |
| auto[1] |
2894471 |
1 |
|
|
T1 |
247 |
|
T12 |
9896 |
|
T13 |
91510 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9072102 |
1 |
|
|
T1 |
1233 |
|
T11 |
421 |
|
T12 |
28252 |
| auto[1] |
7178027 |
1 |
|
|
T1 |
1177 |
|
T12 |
22871 |
|
T13 |
240195 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2140037 |
1 |
|
|
T1 |
434 |
|
T12 |
5974 |
|
T13 |
75466 |
| auto[1] |
auto[0] |
auto[1] |
1449183 |
1 |
|
|
T1 |
129 |
|
T12 |
4749 |
|
T13 |
46178 |
| auto[1] |
auto[1] |
auto[0] |
2143519 |
1 |
|
|
T1 |
496 |
|
T12 |
7001 |
|
T13 |
73219 |
| auto[1] |
auto[1] |
auto[1] |
1445288 |
1 |
|
|
T1 |
118 |
|
T12 |
5147 |
|
T13 |
45332 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |