Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9059484 |
1 |
|
|
T1 |
1042 |
|
T11 |
421 |
|
T12 |
27765 |
| auto[1] |
7190645 |
1 |
|
|
T1 |
1368 |
|
T12 |
23358 |
|
T13 |
242286 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13342602 |
1 |
|
|
T1 |
2238 |
|
T11 |
421 |
|
T12 |
41288 |
| auto[1] |
2907527 |
1 |
|
|
T1 |
172 |
|
T12 |
9835 |
|
T13 |
90044 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9039279 |
1 |
|
|
T1 |
1477 |
|
T11 |
421 |
|
T12 |
27877 |
| auto[1] |
7210850 |
1 |
|
|
T1 |
933 |
|
T12 |
23246 |
|
T13 |
235590 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2148860 |
1 |
|
|
T1 |
339 |
|
T12 |
6869 |
|
T13 |
72996 |
| auto[1] |
auto[0] |
auto[1] |
1451784 |
1 |
|
|
T1 |
94 |
|
T12 |
4906 |
|
T13 |
45055 |
| auto[1] |
auto[1] |
auto[0] |
2154463 |
1 |
|
|
T1 |
422 |
|
T12 |
6542 |
|
T13 |
72550 |
| auto[1] |
auto[1] |
auto[1] |
1455743 |
1 |
|
|
T1 |
78 |
|
T12 |
4929 |
|
T13 |
44989 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |