Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9045323 |
1 |
|
|
T1 |
1060 |
|
T11 |
421 |
|
T12 |
27983 |
| auto[1] |
7204806 |
1 |
|
|
T1 |
1350 |
|
T12 |
23140 |
|
T13 |
245603 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15329663 |
1 |
|
|
T1 |
2357 |
|
T11 |
421 |
|
T12 |
47947 |
| auto[1] |
920466 |
1 |
|
|
T1 |
53 |
|
T12 |
3176 |
|
T13 |
30111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9085549 |
1 |
|
|
T1 |
1096 |
|
T11 |
421 |
|
T12 |
28894 |
| auto[1] |
7164580 |
1 |
|
|
T1 |
1314 |
|
T12 |
22229 |
|
T13 |
232815 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3108296 |
1 |
|
|
T1 |
569 |
|
T12 |
9616 |
|
T13 |
99144 |
| auto[1] |
auto[0] |
auto[1] |
459085 |
1 |
|
|
T1 |
27 |
|
T12 |
1546 |
|
T13 |
14695 |
| auto[1] |
auto[1] |
auto[0] |
3135818 |
1 |
|
|
T1 |
692 |
|
T12 |
9437 |
|
T13 |
103560 |
| auto[1] |
auto[1] |
auto[1] |
461381 |
1 |
|
|
T1 |
26 |
|
T12 |
1630 |
|
T13 |
15416 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |