Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9034858 |
1 |
|
|
T1 |
896 |
|
T11 |
421 |
|
T12 |
28853 |
| auto[1] |
7215271 |
1 |
|
|
T1 |
1514 |
|
T12 |
22270 |
|
T13 |
233501 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15326176 |
1 |
|
|
T1 |
2357 |
|
T11 |
421 |
|
T12 |
47984 |
| auto[1] |
923953 |
1 |
|
|
T1 |
53 |
|
T12 |
3139 |
|
T13 |
31499 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9063954 |
1 |
|
|
T1 |
1365 |
|
T11 |
421 |
|
T12 |
28690 |
| auto[1] |
7186175 |
1 |
|
|
T1 |
1045 |
|
T12 |
22433 |
|
T13 |
239687 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3134238 |
1 |
|
|
T1 |
310 |
|
T12 |
9621 |
|
T13 |
108122 |
| auto[1] |
auto[0] |
auto[1] |
462911 |
1 |
|
|
T1 |
10 |
|
T12 |
1553 |
|
T13 |
16572 |
| auto[1] |
auto[1] |
auto[0] |
3127984 |
1 |
|
|
T1 |
682 |
|
T12 |
9673 |
|
T13 |
100066 |
| auto[1] |
auto[1] |
auto[1] |
461042 |
1 |
|
|
T1 |
43 |
|
T12 |
1586 |
|
T13 |
14927 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |