Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9032257 |
1 |
|
|
T1 |
1124 |
|
T11 |
421 |
|
T12 |
27608 |
| auto[1] |
7217872 |
1 |
|
|
T1 |
1286 |
|
T12 |
23515 |
|
T13 |
236392 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15327658 |
1 |
|
|
T1 |
2362 |
|
T11 |
421 |
|
T12 |
47845 |
| auto[1] |
922471 |
1 |
|
|
T1 |
48 |
|
T12 |
3278 |
|
T13 |
30803 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9072005 |
1 |
|
|
T1 |
1161 |
|
T11 |
421 |
|
T12 |
28253 |
| auto[1] |
7178124 |
1 |
|
|
T1 |
1249 |
|
T12 |
22870 |
|
T13 |
236552 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3115323 |
1 |
|
|
T1 |
570 |
|
T12 |
9289 |
|
T13 |
105657 |
| auto[1] |
auto[0] |
auto[1] |
459732 |
1 |
|
|
T1 |
22 |
|
T12 |
1581 |
|
T13 |
15900 |
| auto[1] |
auto[1] |
auto[0] |
3140330 |
1 |
|
|
T1 |
631 |
|
T12 |
10303 |
|
T13 |
100092 |
| auto[1] |
auto[1] |
auto[1] |
462739 |
1 |
|
|
T1 |
26 |
|
T12 |
1697 |
|
T13 |
14903 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |