Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9078230 |
1 |
|
|
T1 |
1193 |
|
T11 |
421 |
|
T12 |
26786 |
| auto[1] |
7171899 |
1 |
|
|
T1 |
1217 |
|
T12 |
24337 |
|
T13 |
241301 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15320253 |
1 |
|
|
T1 |
2366 |
|
T11 |
421 |
|
T12 |
48048 |
| auto[1] |
929876 |
1 |
|
|
T1 |
44 |
|
T12 |
3075 |
|
T13 |
31325 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9021835 |
1 |
|
|
T1 |
1230 |
|
T11 |
421 |
|
T12 |
28885 |
| auto[1] |
7228294 |
1 |
|
|
T1 |
1180 |
|
T12 |
22238 |
|
T13 |
239536 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3160793 |
1 |
|
|
T1 |
520 |
|
T12 |
8892 |
|
T13 |
106803 |
| auto[1] |
auto[0] |
auto[1] |
467550 |
1 |
|
|
T1 |
19 |
|
T12 |
1431 |
|
T13 |
16123 |
| auto[1] |
auto[1] |
auto[0] |
3137625 |
1 |
|
|
T1 |
616 |
|
T12 |
10271 |
|
T13 |
101408 |
| auto[1] |
auto[1] |
auto[1] |
462326 |
1 |
|
|
T1 |
25 |
|
T12 |
1644 |
|
T13 |
15202 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |