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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
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T762 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1059461628 Jul 09 05:04:06 PM PDT 24 Jul 09 05:04:08 PM PDT 24 11368404 ps
T86 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2611425707 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:54 PM PDT 24 63197302 ps
T763 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1137541702 Jul 09 05:03:59 PM PDT 24 Jul 09 05:04:03 PM PDT 24 243725768 ps
T764 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.315059711 Jul 09 05:03:58 PM PDT 24 Jul 09 05:04:02 PM PDT 24 160414957 ps
T765 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3117008081 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:56 PM PDT 24 120892481 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2724534166 Jul 09 05:03:54 PM PDT 24 Jul 09 05:03:58 PM PDT 24 45742386 ps
T36 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3925047600 Jul 09 05:03:50 PM PDT 24 Jul 09 05:03:54 PM PDT 24 100172592 ps
T767 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.41871750 Jul 09 05:03:54 PM PDT 24 Jul 09 05:03:58 PM PDT 24 46798220 ps
T768 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2484657029 Jul 09 05:04:02 PM PDT 24 Jul 09 05:04:05 PM PDT 24 41027138 ps
T769 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2538983502 Jul 09 05:03:53 PM PDT 24 Jul 09 05:03:57 PM PDT 24 188760969 ps
T770 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3327317479 Jul 09 05:03:49 PM PDT 24 Jul 09 05:03:52 PM PDT 24 392225035 ps
T771 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1111882653 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:56 PM PDT 24 246371912 ps
T772 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3630519753 Jul 09 05:03:59 PM PDT 24 Jul 09 05:04:02 PM PDT 24 30365827 ps
T100 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.661116689 Jul 09 05:03:50 PM PDT 24 Jul 09 05:03:53 PM PDT 24 230662074 ps
T773 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2173400921 Jul 09 05:03:50 PM PDT 24 Jul 09 05:03:56 PM PDT 24 267112835 ps
T774 /workspace/coverage/cover_reg_top/22.gpio_intr_test.770816745 Jul 09 05:04:06 PM PDT 24 Jul 09 05:04:08 PM PDT 24 44338536 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1232793501 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:56 PM PDT 24 16200853 ps
T776 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.167356485 Jul 09 05:03:48 PM PDT 24 Jul 09 05:03:51 PM PDT 24 438380248 ps
T777 /workspace/coverage/cover_reg_top/12.gpio_intr_test.4252173909 Jul 09 05:03:57 PM PDT 24 Jul 09 05:04:01 PM PDT 24 29075873 ps
T778 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2696107446 Jul 09 05:03:53 PM PDT 24 Jul 09 05:03:58 PM PDT 24 138883102 ps
T72 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4052831353 Jul 09 05:03:54 PM PDT 24 Jul 09 05:03:58 PM PDT 24 22267546 ps
T779 /workspace/coverage/cover_reg_top/40.gpio_intr_test.4189545992 Jul 09 05:04:05 PM PDT 24 Jul 09 05:04:06 PM PDT 24 25283833 ps
T780 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2246911916 Jul 09 05:03:50 PM PDT 24 Jul 09 05:03:53 PM PDT 24 61631405 ps
T73 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3061966434 Jul 09 05:03:53 PM PDT 24 Jul 09 05:03:57 PM PDT 24 28716463 ps
T781 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1632558400 Jul 09 05:04:01 PM PDT 24 Jul 09 05:04:03 PM PDT 24 11355617 ps
T782 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2551883418 Jul 09 05:04:04 PM PDT 24 Jul 09 05:04:05 PM PDT 24 57811966 ps
T783 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4105381781 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:55 PM PDT 24 87907227 ps
T784 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1013522569 Jul 09 05:04:05 PM PDT 24 Jul 09 05:04:07 PM PDT 24 63026316 ps
T785 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3383312965 Jul 09 05:03:54 PM PDT 24 Jul 09 05:03:58 PM PDT 24 16395492 ps
T786 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3639269410 Jul 09 05:03:53 PM PDT 24 Jul 09 05:03:56 PM PDT 24 45921859 ps
T787 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.454007205 Jul 09 05:03:48 PM PDT 24 Jul 09 05:03:51 PM PDT 24 257892418 ps
T788 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1061459158 Jul 09 05:04:03 PM PDT 24 Jul 09 05:04:05 PM PDT 24 44783457 ps
T789 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3397621667 Jul 09 05:03:54 PM PDT 24 Jul 09 05:03:58 PM PDT 24 16819065 ps
T790 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1600016510 Jul 09 05:03:59 PM PDT 24 Jul 09 05:04:04 PM PDT 24 572774930 ps
T791 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2294890428 Jul 09 05:03:49 PM PDT 24 Jul 09 05:03:51 PM PDT 24 143254187 ps
T792 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3343434709 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:57 PM PDT 24 407273779 ps
T793 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4199599282 Jul 09 05:03:57 PM PDT 24 Jul 09 05:04:01 PM PDT 24 30008073 ps
T794 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1975089569 Jul 09 05:04:03 PM PDT 24 Jul 09 05:04:05 PM PDT 24 31091699 ps
T795 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3785612303 Jul 09 05:04:02 PM PDT 24 Jul 09 05:04:04 PM PDT 24 30090623 ps
T796 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2199335407 Jul 09 05:04:05 PM PDT 24 Jul 09 05:04:06 PM PDT 24 37649348 ps
T797 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.993349671 Jul 09 05:04:00 PM PDT 24 Jul 09 05:04:02 PM PDT 24 34795198 ps
T798 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.156731936 Jul 09 05:03:59 PM PDT 24 Jul 09 05:04:02 PM PDT 24 50900562 ps
T799 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4106775291 Jul 09 05:04:00 PM PDT 24 Jul 09 05:04:03 PM PDT 24 100801255 ps
T800 /workspace/coverage/cover_reg_top/27.gpio_intr_test.459910278 Jul 09 05:04:10 PM PDT 24 Jul 09 05:04:12 PM PDT 24 15369425 ps
T801 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2914501506 Jul 09 05:03:49 PM PDT 24 Jul 09 05:03:53 PM PDT 24 196360651 ps
T802 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3520981764 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:55 PM PDT 24 10826837 ps
T74 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.215527126 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:54 PM PDT 24 115963985 ps
T803 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1297197126 Jul 09 05:03:53 PM PDT 24 Jul 09 05:03:57 PM PDT 24 31461970 ps
T804 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1220403845 Jul 09 05:04:06 PM PDT 24 Jul 09 05:04:08 PM PDT 24 53010488 ps
T37 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1401838033 Jul 09 05:04:02 PM PDT 24 Jul 09 05:04:05 PM PDT 24 80513309 ps
T805 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3055441739 Jul 09 05:03:55 PM PDT 24 Jul 09 05:04:00 PM PDT 24 105317996 ps
T806 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2623279378 Jul 09 05:03:45 PM PDT 24 Jul 09 05:03:46 PM PDT 24 111329437 ps
T807 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.735951909 Jul 09 05:04:03 PM PDT 24 Jul 09 05:04:06 PM PDT 24 51053183 ps
T808 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1151993238 Jul 09 05:03:43 PM PDT 24 Jul 09 05:03:45 PM PDT 24 29885030 ps
T809 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3441976127 Jul 09 05:04:01 PM PDT 24 Jul 09 05:04:03 PM PDT 24 83812345 ps
T810 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4260612336 Jul 09 05:03:45 PM PDT 24 Jul 09 05:03:47 PM PDT 24 34169112 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.26904580 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:56 PM PDT 24 30851220 ps
T812 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3097190289 Jul 09 05:04:02 PM PDT 24 Jul 09 05:04:04 PM PDT 24 37407136 ps
T813 /workspace/coverage/cover_reg_top/46.gpio_intr_test.863596912 Jul 09 05:04:03 PM PDT 24 Jul 09 05:04:05 PM PDT 24 14249944 ps
T38 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.663808549 Jul 09 05:03:53 PM PDT 24 Jul 09 05:03:57 PM PDT 24 294486657 ps
T814 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2953891721 Jul 09 05:03:53 PM PDT 24 Jul 09 05:03:57 PM PDT 24 53623677 ps
T815 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2978895445 Jul 09 05:03:49 PM PDT 24 Jul 09 05:03:51 PM PDT 24 17317183 ps
T816 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2499555901 Jul 09 05:04:09 PM PDT 24 Jul 09 05:04:10 PM PDT 24 63213878 ps
T817 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.918292799 Jul 09 05:03:59 PM PDT 24 Jul 09 05:04:02 PM PDT 24 62328172 ps
T818 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4156261489 Jul 09 05:03:54 PM PDT 24 Jul 09 05:03:59 PM PDT 24 30332863 ps
T819 /workspace/coverage/cover_reg_top/42.gpio_intr_test.966867312 Jul 09 05:04:06 PM PDT 24 Jul 09 05:04:08 PM PDT 24 31507868 ps
T820 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.997265604 Jul 09 05:03:57 PM PDT 24 Jul 09 05:04:01 PM PDT 24 41351092 ps
T821 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3058698891 Jul 09 05:04:05 PM PDT 24 Jul 09 05:04:07 PM PDT 24 40660877 ps
T822 /workspace/coverage/cover_reg_top/28.gpio_intr_test.4082794343 Jul 09 05:04:04 PM PDT 24 Jul 09 05:04:05 PM PDT 24 15344550 ps
T823 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1354452215 Jul 09 05:04:27 PM PDT 24 Jul 09 05:04:31 PM PDT 24 1341874075 ps
T824 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.342848122 Jul 09 05:03:49 PM PDT 24 Jul 09 05:03:50 PM PDT 24 17873046 ps
T75 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1134172641 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:55 PM PDT 24 11811776 ps
T825 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2693504413 Jul 09 05:04:06 PM PDT 24 Jul 09 05:04:07 PM PDT 24 90016380 ps
T826 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.346429262 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:56 PM PDT 24 266258117 ps
T827 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2339277538 Jul 09 05:03:54 PM PDT 24 Jul 09 05:04:00 PM PDT 24 57567614 ps
T828 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4184564864 Jul 09 05:03:55 PM PDT 24 Jul 09 05:04:00 PM PDT 24 14909848 ps
T829 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1680636618 Jul 09 05:03:55 PM PDT 24 Jul 09 05:04:00 PM PDT 24 24657979 ps
T830 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3948772191 Jul 09 05:03:50 PM PDT 24 Jul 09 05:03:52 PM PDT 24 52122686 ps
T77 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.404485935 Jul 09 05:03:47 PM PDT 24 Jul 09 05:03:49 PM PDT 24 56348377 ps
T831 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1959891394 Jul 09 05:03:49 PM PDT 24 Jul 09 05:03:53 PM PDT 24 204238107 ps
T832 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1784214476 Jul 09 05:04:08 PM PDT 24 Jul 09 05:04:09 PM PDT 24 17983944 ps
T76 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1709787269 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:55 PM PDT 24 31330789 ps
T833 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1120604060 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:56 PM PDT 24 58454822 ps
T834 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1010544823 Jul 09 05:04:00 PM PDT 24 Jul 09 05:04:03 PM PDT 24 74220386 ps
T835 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2952093760 Jul 09 05:04:01 PM PDT 24 Jul 09 05:04:03 PM PDT 24 29119481 ps
T836 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3261655381 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:56 PM PDT 24 57483187 ps
T837 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1742547447 Jul 09 05:03:48 PM PDT 24 Jul 09 05:03:49 PM PDT 24 84494655 ps
T838 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2217711567 Jul 09 05:04:01 PM PDT 24 Jul 09 05:04:03 PM PDT 24 15644395 ps
T839 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3103029359 Jul 09 05:03:52 PM PDT 24 Jul 09 05:03:57 PM PDT 24 119973124 ps
T840 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3993275471 Jul 09 05:04:00 PM PDT 24 Jul 09 05:04:03 PM PDT 24 45446175 ps
T841 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3173435754 Jul 09 05:03:51 PM PDT 24 Jul 09 05:03:56 PM PDT 24 27689140 ps
T842 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2487037956 Jul 09 05:03:48 PM PDT 24 Jul 09 05:03:49 PM PDT 24 42794616 ps
T843 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1657429810 Jul 09 05:04:08 PM PDT 24 Jul 09 05:04:09 PM PDT 24 38516994 ps
T844 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.368866797 Jul 09 05:03:57 PM PDT 24 Jul 09 05:04:01 PM PDT 24 39961675 ps
T845 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1805182717 Jul 09 05:03:56 PM PDT 24 Jul 09 05:04:01 PM PDT 24 84306813 ps
T846 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.617557729 Jul 09 05:03:48 PM PDT 24 Jul 09 05:03:50 PM PDT 24 156169310 ps
T847 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3230241509 Jul 09 05:04:09 PM PDT 24 Jul 09 05:04:11 PM PDT 24 152759870 ps
T848 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3030130444 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:21 PM PDT 24 60236498 ps
T849 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1037566911 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:26 PM PDT 24 46624443 ps
T850 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2176702281 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:26 PM PDT 24 73322034 ps
T851 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.544662080 Jul 09 05:04:08 PM PDT 24 Jul 09 05:04:10 PM PDT 24 253735497 ps
T852 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2889290997 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:21 PM PDT 24 334551464 ps
T853 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2436169681 Jul 09 05:04:14 PM PDT 24 Jul 09 05:04:16 PM PDT 24 40984364 ps
T854 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3064602884 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:26 PM PDT 24 65819772 ps
T855 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1075535816 Jul 09 05:04:22 PM PDT 24 Jul 09 05:04:24 PM PDT 24 166203914 ps
T856 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4173840989 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:22 PM PDT 24 31881676 ps
T857 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3426578299 Jul 09 05:04:22 PM PDT 24 Jul 09 05:04:24 PM PDT 24 40756716 ps
T858 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3969141202 Jul 09 05:04:12 PM PDT 24 Jul 09 05:04:14 PM PDT 24 43110118 ps
T859 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1741647025 Jul 09 05:04:10 PM PDT 24 Jul 09 05:04:12 PM PDT 24 66299078 ps
T860 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3745589469 Jul 09 05:04:18 PM PDT 24 Jul 09 05:04:20 PM PDT 24 61153069 ps
T861 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.183488789 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:30 PM PDT 24 47047541 ps
T862 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4006715918 Jul 09 05:04:14 PM PDT 24 Jul 09 05:04:16 PM PDT 24 57693252 ps
T863 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.941300522 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:21 PM PDT 24 54513997 ps
T864 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.693302043 Jul 09 05:04:18 PM PDT 24 Jul 09 05:04:20 PM PDT 24 115179429 ps
T865 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2469663200 Jul 09 05:04:10 PM PDT 24 Jul 09 05:04:12 PM PDT 24 49729807 ps
T866 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1307927727 Jul 09 05:04:13 PM PDT 24 Jul 09 05:04:16 PM PDT 24 183730447 ps
T867 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3164248041 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:30 PM PDT 24 95691391 ps
T868 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151716813 Jul 09 05:04:10 PM PDT 24 Jul 09 05:04:12 PM PDT 24 59748721 ps
T869 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.234051043 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:22 PM PDT 24 303608693 ps
T870 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1558393940 Jul 09 05:04:16 PM PDT 24 Jul 09 05:04:18 PM PDT 24 377383347 ps
T871 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123782401 Jul 09 05:04:14 PM PDT 24 Jul 09 05:04:16 PM PDT 24 30525552 ps
T872 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3214801071 Jul 09 05:04:14 PM PDT 24 Jul 09 05:04:15 PM PDT 24 34559914 ps
T873 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305150446 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:21 PM PDT 24 146219021 ps
T874 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301571145 Jul 09 05:04:17 PM PDT 24 Jul 09 05:04:19 PM PDT 24 74475366 ps
T875 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.979512517 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:28 PM PDT 24 212995700 ps
T876 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1850237086 Jul 09 05:04:22 PM PDT 24 Jul 09 05:04:23 PM PDT 24 23574845 ps
T877 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2659150893 Jul 09 05:04:27 PM PDT 24 Jul 09 05:04:30 PM PDT 24 212551385 ps
T878 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1201548185 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:22 PM PDT 24 96546981 ps
T879 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4203061644 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:21 PM PDT 24 112652643 ps
T880 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1015441043 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:26 PM PDT 24 340868624 ps
T881 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.296767465 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 80019574 ps
T882 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1594113033 Jul 09 05:04:13 PM PDT 24 Jul 09 05:04:15 PM PDT 24 325002000 ps
T883 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1868049778 Jul 09 05:04:21 PM PDT 24 Jul 09 05:04:23 PM PDT 24 152425594 ps
T884 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2997775409 Jul 09 05:04:09 PM PDT 24 Jul 09 05:04:11 PM PDT 24 91208951 ps
T885 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3251166886 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:22 PM PDT 24 47236528 ps
T886 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1579615483 Jul 09 05:04:08 PM PDT 24 Jul 09 05:04:09 PM PDT 24 24100676 ps
T887 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2943384390 Jul 09 05:04:16 PM PDT 24 Jul 09 05:04:18 PM PDT 24 168335196 ps
T888 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1317312796 Jul 09 05:04:12 PM PDT 24 Jul 09 05:04:14 PM PDT 24 101043384 ps
T889 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.549036129 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:23 PM PDT 24 76469144 ps
T890 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3650203726 Jul 09 05:04:21 PM PDT 24 Jul 09 05:04:23 PM PDT 24 365235460 ps
T891 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2449092451 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:22 PM PDT 24 45935444 ps
T892 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.703651857 Jul 09 05:04:21 PM PDT 24 Jul 09 05:04:23 PM PDT 24 237011703 ps
T893 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4231181283 Jul 09 05:04:16 PM PDT 24 Jul 09 05:04:18 PM PDT 24 102868390 ps
T894 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1712829953 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:26 PM PDT 24 128661491 ps
T895 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1668974061 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:27 PM PDT 24 113476498 ps
T896 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4018164964 Jul 09 05:04:13 PM PDT 24 Jul 09 05:04:16 PM PDT 24 338879639 ps
T897 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2323052612 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:23 PM PDT 24 194063861 ps
T898 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4262200284 Jul 09 05:04:20 PM PDT 24 Jul 09 05:04:23 PM PDT 24 182759756 ps
T899 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3735387390 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:30 PM PDT 24 125561440 ps
T900 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1194759091 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:26 PM PDT 24 66770001 ps
T901 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1869691523 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 132454430 ps
T902 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.54044941 Jul 09 05:04:21 PM PDT 24 Jul 09 05:04:23 PM PDT 24 180995996 ps
T903 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1719396896 Jul 09 05:04:12 PM PDT 24 Jul 09 05:04:15 PM PDT 24 29190658 ps
T904 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2317467829 Jul 09 05:04:09 PM PDT 24 Jul 09 05:04:11 PM PDT 24 64868637 ps
T905 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3156376158 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:31 PM PDT 24 86656312 ps
T906 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4242274857 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:30 PM PDT 24 116336260 ps
T907 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4078605209 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:27 PM PDT 24 172152753 ps
T908 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1705269345 Jul 09 05:04:17 PM PDT 24 Jul 09 05:04:19 PM PDT 24 84162887 ps
T909 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2138608979 Jul 09 05:04:15 PM PDT 24 Jul 09 05:04:17 PM PDT 24 76205776 ps
T910 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2237832249 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:20 PM PDT 24 92636171 ps
T911 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4096912523 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:27 PM PDT 24 86285158 ps
T912 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1844303948 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:20 PM PDT 24 162314941 ps
T913 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3198944240 Jul 09 05:04:11 PM PDT 24 Jul 09 05:04:13 PM PDT 24 47260265 ps
T914 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.768308169 Jul 09 05:04:13 PM PDT 24 Jul 09 05:04:15 PM PDT 24 138689112 ps
T915 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127537737 Jul 09 05:04:11 PM PDT 24 Jul 09 05:04:13 PM PDT 24 84039474 ps
T916 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2396999988 Jul 09 05:04:14 PM PDT 24 Jul 09 05:04:16 PM PDT 24 174811768 ps
T917 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1729768845 Jul 09 05:04:10 PM PDT 24 Jul 09 05:04:12 PM PDT 24 394512713 ps
T918 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2907838163 Jul 09 05:04:11 PM PDT 24 Jul 09 05:04:14 PM PDT 24 41417591 ps
T919 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2573017372 Jul 09 05:04:17 PM PDT 24 Jul 09 05:04:18 PM PDT 24 174401833 ps
T920 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3764888712 Jul 09 05:04:16 PM PDT 24 Jul 09 05:04:18 PM PDT 24 58788050 ps
T921 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2100686077 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:21 PM PDT 24 65799327 ps
T922 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.710980273 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 49207407 ps
T923 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2989609361 Jul 09 05:04:21 PM PDT 24 Jul 09 05:04:23 PM PDT 24 191835689 ps
T924 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3847585525 Jul 09 05:04:09 PM PDT 24 Jul 09 05:04:11 PM PDT 24 304793887 ps
T925 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1155317819 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 85477724 ps
T926 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3862046380 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:30 PM PDT 24 72920011 ps
T927 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3339404416 Jul 09 05:04:21 PM PDT 24 Jul 09 05:04:23 PM PDT 24 46076068 ps
T928 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59705379 Jul 09 05:04:11 PM PDT 24 Jul 09 05:04:13 PM PDT 24 367614855 ps
T929 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1865570808 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 394151949 ps
T930 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1069500071 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:28 PM PDT 24 42921541 ps
T931 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458582222 Jul 09 05:04:13 PM PDT 24 Jul 09 05:04:15 PM PDT 24 115111997 ps
T932 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1069211161 Jul 09 05:04:22 PM PDT 24 Jul 09 05:04:24 PM PDT 24 37377238 ps
T933 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.912017456 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:26 PM PDT 24 193803015 ps
T934 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1831525363 Jul 09 05:04:15 PM PDT 24 Jul 09 05:04:17 PM PDT 24 49534935 ps
T935 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2581950739 Jul 09 05:04:18 PM PDT 24 Jul 09 05:04:19 PM PDT 24 48832617 ps
T936 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574055687 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:28 PM PDT 24 275569394 ps
T937 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2652957139 Jul 09 05:04:18 PM PDT 24 Jul 09 05:04:20 PM PDT 24 41465433 ps
T938 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2328335560 Jul 09 05:04:12 PM PDT 24 Jul 09 05:04:15 PM PDT 24 664196272 ps
T939 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1270613631 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 272035814 ps
T940 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725678255 Jul 09 05:04:11 PM PDT 24 Jul 09 05:04:13 PM PDT 24 40753993 ps
T941 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3562432209 Jul 09 05:04:08 PM PDT 24 Jul 09 05:04:10 PM PDT 24 212072542 ps
T942 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2186303807 Jul 09 05:04:19 PM PDT 24 Jul 09 05:04:22 PM PDT 24 166194475 ps
T943 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.793372818 Jul 09 05:04:14 PM PDT 24 Jul 09 05:04:16 PM PDT 24 125904125 ps
T944 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3413951025 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 591637514 ps
T945 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.626891780 Jul 09 05:04:16 PM PDT 24 Jul 09 05:04:18 PM PDT 24 81322026 ps
T946 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3975801746 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:29 PM PDT 24 154399965 ps

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.4288828565
Short name T13
Test name
Test status
Simulation time 50508325345 ps
CPU time 1235.55 seconds
Started Jul 09 04:39:36 PM PDT 24
Finished Jul 09 05:00:12 PM PDT 24
Peak memory 198680 kb
Host smart-4ba42014-f091-4927-a2ee-029d22e3aede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4288828565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.4288828565
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1727454151
Short name T102
Test name
Test status
Simulation time 461228113 ps
CPU time 3.12 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:51 PM PDT 24
Peak memory 198384 kb
Host smart-d244369c-7061-4f08-ade6-56a49944c13b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727454151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1727454151
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3348834877
Short name T12
Test name
Test status
Simulation time 89117875072 ps
CPU time 77.45 seconds
Started Jul 09 04:38:28 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 198748 kb
Host smart-0484fd16-2afb-4e05-9a1e-6d9c64c0aa41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348834877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3348834877
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3393144390
Short name T29
Test name
Test status
Simulation time 109957259 ps
CPU time 0.82 seconds
Started Jul 09 04:37:37 PM PDT 24
Finished Jul 09 04:37:39 PM PDT 24
Peak memory 214172 kb
Host smart-f08b96e6-22a8-4325-b4c8-8f825f45cd67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393144390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3393144390
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2665226454
Short name T62
Test name
Test status
Simulation time 27037342 ps
CPU time 0.8 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 196640 kb
Host smart-50426eb4-be0f-4416-97c3-c4167d113f8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665226454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2665226454
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2145525121
Short name T10
Test name
Test status
Simulation time 10864397298 ps
CPU time 62.52 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 04:39:40 PM PDT 24
Peak memory 198740 kb
Host smart-6407a13b-7ee6-46a3-ae87-01fd100be6ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145525121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2145525121
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1501456801
Short name T28
Test name
Test status
Simulation time 377462176 ps
CPU time 1.43 seconds
Started Jul 09 05:03:58 PM PDT 24
Finished Jul 09 05:04:02 PM PDT 24
Peak memory 198668 kb
Host smart-2017e278-b8a7-452f-ba01-662ae4ada948
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501456801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1501456801
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1964557040
Short name T162
Test name
Test status
Simulation time 18522365 ps
CPU time 0.57 seconds
Started Jul 09 04:37:40 PM PDT 24
Finished Jul 09 04:37:41 PM PDT 24
Peak memory 194720 kb
Host smart-827212c6-4164-4319-8069-8393b20a2167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964557040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1964557040
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1709787269
Short name T76
Test name
Test status
Simulation time 31330789 ps
CPU time 0.8 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 196904 kb
Host smart-3d35aa3f-2996-4100-bcb3-64b8d69e1a45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709787269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1709787269
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1750176462
Short name T82
Test name
Test status
Simulation time 36929659 ps
CPU time 0.8 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 196472 kb
Host smart-a6961c3f-5a5d-4d16-a0e5-2848c88899d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750176462 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1750176462
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3103029359
Short name T839
Test name
Test status
Simulation time 119973124 ps
CPU time 1.45 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 198632 kb
Host smart-92636795-3e63-4ae1-9593-fd74f9c0c51e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103029359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3103029359
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.167356485
Short name T776
Test name
Test status
Simulation time 438380248 ps
CPU time 1.39 seconds
Started Jul 09 05:03:48 PM PDT 24
Finished Jul 09 05:03:51 PM PDT 24
Peak memory 198624 kb
Host smart-c2b309c8-34d5-4a6e-85d6-cbe153023fac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167356485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.167356485
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2392243749
Short name T71
Test name
Test status
Simulation time 351244416 ps
CPU time 3.07 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:49 PM PDT 24
Peak memory 198548 kb
Host smart-4067648c-cfcf-4915-8436-383a5b273737
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392243749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2392243749
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3352971233
Short name T747
Test name
Test status
Simulation time 48740062 ps
CPU time 0.61 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 195068 kb
Host smart-c8cae2b1-0af1-49e4-ad87-48170bbeab8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352971233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3352971233
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4260612336
Short name T810
Test name
Test status
Simulation time 34169112 ps
CPU time 0.74 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:47 PM PDT 24
Peak memory 198532 kb
Host smart-d6dfeb97-3b65-491c-8cc0-ed6c438f0295
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260612336 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.4260612336
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.215527126
Short name T74
Test name
Test status
Simulation time 115963985 ps
CPU time 0.63 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:54 PM PDT 24
Peak memory 195168 kb
Host smart-4515e366-2487-4866-bf58-fbc8626b3b6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215527126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.215527126
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1297197126
Short name T803
Test name
Test status
Simulation time 31461970 ps
CPU time 0.64 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 194356 kb
Host smart-5ceddc50-0389-473d-af64-6d7def1852e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297197126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1297197126
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2623279378
Short name T806
Test name
Test status
Simulation time 111329437 ps
CPU time 0.81 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 197428 kb
Host smart-e71bbf97-e469-4134-aacb-c1be58fdf46e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623279378 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2623279378
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.346429262
Short name T826
Test name
Test status
Simulation time 266258117 ps
CPU time 2.39 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 198624 kb
Host smart-6f73ccd1-70db-4a42-88ad-81c487079a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346429262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.346429262
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.967366769
Short name T99
Test name
Test status
Simulation time 21105284 ps
CPU time 0.71 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:47 PM PDT 24
Peak memory 195172 kb
Host smart-8ee1821d-fbb2-46df-b432-93e6d89b5ee5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967366769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.967366769
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2339277538
Short name T827
Test name
Test status
Simulation time 57567614 ps
CPU time 2.36 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 198580 kb
Host smart-d20a8b7b-90b1-4ba8-a83a-23261f91d9b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339277538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2339277538
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2487037956
Short name T842
Test name
Test status
Simulation time 42794616 ps
CPU time 0.63 seconds
Started Jul 09 05:03:48 PM PDT 24
Finished Jul 09 05:03:49 PM PDT 24
Peak memory 194948 kb
Host smart-d3763902-f8aa-4e85-a8a4-aeb23f7479b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487037956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2487037956
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1664108948
Short name T720
Test name
Test status
Simulation time 67739190 ps
CPU time 1.09 seconds
Started Jul 09 05:03:43 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 198524 kb
Host smart-13779944-8a08-449d-9401-bd73f5e417f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664108948 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1664108948
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.41871750
Short name T767
Test name
Test status
Simulation time 46798220 ps
CPU time 0.6 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 194904 kb
Host smart-b4ca2615-d0e7-4c4c-b239-00d6b22fd2c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_c
sr_rw.41871750
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3869446270
Short name T742
Test name
Test status
Simulation time 17892180 ps
CPU time 0.64 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:51 PM PDT 24
Peak memory 194388 kb
Host smart-d9d41780-58b8-4de3-9147-56d0b9147df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869446270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3869446270
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1151993238
Short name T808
Test name
Test status
Simulation time 29885030 ps
CPU time 0.79 seconds
Started Jul 09 05:03:43 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 196524 kb
Host smart-894facce-930e-4cce-b929-cba7a219f03c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151993238 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1151993238
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1600345169
Short name T759
Test name
Test status
Simulation time 183022126 ps
CPU time 1.93 seconds
Started Jul 09 05:03:48 PM PDT 24
Finished Jul 09 05:03:50 PM PDT 24
Peak memory 198648 kb
Host smart-b8cead45-6c05-49fe-98a3-297756c365ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600345169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1600345169
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3454378456
Short name T746
Test name
Test status
Simulation time 193041605 ps
CPU time 1.47 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:48 PM PDT 24
Peak memory 198592 kb
Host smart-93b485cf-2849-4290-8548-ddb6d1b12b46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454378456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3454378456
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3173435754
Short name T841
Test name
Test status
Simulation time 27689140 ps
CPU time 1.34 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 198692 kb
Host smart-5f841725-54d3-49a3-862b-6d537b7613b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173435754 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3173435754
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3383312965
Short name T785
Test name
Test status
Simulation time 16395492 ps
CPU time 0.61 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 195072 kb
Host smart-be20593a-0ce3-4908-acc1-6baede62e3b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383312965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3383312965
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3125268243
Short name T736
Test name
Test status
Simulation time 57078234 ps
CPU time 0.58 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 194208 kb
Host smart-557ef3b2-b14d-4376-b64e-d77c920b250a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125268243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3125268243
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3155625592
Short name T734
Test name
Test status
Simulation time 50935500 ps
CPU time 2.57 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 198556 kb
Host smart-2077f469-6ec5-4632-8a2d-7b8b53fc829f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155625592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3155625592
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1021387605
Short name T35
Test name
Test status
Simulation time 134150213 ps
CPU time 1.47 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:59 PM PDT 24
Peak memory 198580 kb
Host smart-b164f980-516c-4976-a790-60a1c47f959f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021387605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1021387605
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.993349671
Short name T797
Test name
Test status
Simulation time 34795198 ps
CPU time 0.87 seconds
Started Jul 09 05:04:00 PM PDT 24
Finished Jul 09 05:04:02 PM PDT 24
Peak memory 198464 kb
Host smart-f49a8160-33d0-4484-9029-2e8f788a61ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993349671 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.993349671
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3564625050
Short name T748
Test name
Test status
Simulation time 16173997 ps
CPU time 0.62 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 195144 kb
Host smart-f8a0c241-5eb9-46b6-86a6-0145f6ef0198
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564625050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3564625050
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1786769921
Short name T724
Test name
Test status
Simulation time 16203294 ps
CPU time 0.63 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 194936 kb
Host smart-ba48a88d-59c6-4f4d-8a87-0e3ace0b0956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786769921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1786769921
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4184564864
Short name T828
Test name
Test status
Simulation time 14909848 ps
CPU time 0.64 seconds
Started Jul 09 05:03:55 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 195320 kb
Host smart-f5936997-592c-4693-b177-32512689ffb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184564864 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4184564864
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3512457078
Short name T722
Test name
Test status
Simulation time 56645723 ps
CPU time 1.7 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:59 PM PDT 24
Peak memory 198616 kb
Host smart-bc7169ec-67d8-46a9-b0c4-9e41b12d4a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512457078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3512457078
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.329177008
Short name T27
Test name
Test status
Simulation time 364215871 ps
CPU time 1.44 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 198624 kb
Host smart-ab27d3e4-14f3-49ea-a579-7a8c4b98c196
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329177008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.329177008
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1111882653
Short name T771
Test name
Test status
Simulation time 246371912 ps
CPU time 0.73 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 197984 kb
Host smart-9ba31482-4b17-41d7-b574-7ea81a496160
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111882653 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1111882653
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1680636618
Short name T829
Test name
Test status
Simulation time 24657979 ps
CPU time 0.64 seconds
Started Jul 09 05:03:55 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 195584 kb
Host smart-75320c44-a1f2-4193-8d77-ac0764c643f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680636618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1680636618
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.4252173909
Short name T777
Test name
Test status
Simulation time 29075873 ps
CPU time 0.62 seconds
Started Jul 09 05:03:57 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 194288 kb
Host smart-7e3c4752-6750-4073-bc75-73fee5b71023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252173909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.4252173909
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2882087874
Short name T80
Test name
Test status
Simulation time 20236495 ps
CPU time 0.64 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 194968 kb
Host smart-c04c9b6c-f4a8-49dd-b47a-4e379f82695a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882087874 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2882087874
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1805182717
Short name T845
Test name
Test status
Simulation time 84306813 ps
CPU time 1.35 seconds
Started Jul 09 05:03:56 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 198576 kb
Host smart-d7edf862-9a3f-45bb-b47b-f4319cfd1c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805182717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1805182717
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2236206125
Short name T39
Test name
Test status
Simulation time 556317386 ps
CPU time 1.47 seconds
Started Jul 09 05:03:59 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 198428 kb
Host smart-11a8dd9c-2b31-464c-92b7-8142373d3940
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236206125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2236206125
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.156731936
Short name T798
Test name
Test status
Simulation time 50900562 ps
CPU time 0.79 seconds
Started Jul 09 05:03:59 PM PDT 24
Finished Jul 09 05:04:02 PM PDT 24
Peak memory 198360 kb
Host smart-b0912210-4d2c-437f-b968-4cfae044c7ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156731936 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.156731936
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.368866797
Short name T844
Test name
Test status
Simulation time 39961675 ps
CPU time 0.59 seconds
Started Jul 09 05:03:57 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 195704 kb
Host smart-05beec10-2d07-478f-af1a-1f42e20fde8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368866797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.368866797
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3485471765
Short name T732
Test name
Test status
Simulation time 22548522 ps
CPU time 0.61 seconds
Started Jul 09 05:03:56 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 194332 kb
Host smart-b2b7a10f-7640-4111-b040-bcffa2b13a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485471765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3485471765
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1196277141
Short name T83
Test name
Test status
Simulation time 110367476 ps
CPU time 0.68 seconds
Started Jul 09 05:03:58 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 195136 kb
Host smart-01f5babf-a552-41dc-990f-55d4873aadfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196277141 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1196277141
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2605493679
Short name T727
Test name
Test status
Simulation time 40563398 ps
CPU time 2.1 seconds
Started Jul 09 05:03:58 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 198620 kb
Host smart-fee706a9-0cd4-4b24-bbd7-123af6c17b83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605493679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2605493679
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.970142580
Short name T26
Test name
Test status
Simulation time 40724911 ps
CPU time 0.9 seconds
Started Jul 09 05:03:56 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 198100 kb
Host smart-45c81353-0728-4d47-aacb-cd35d034ad7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970142580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.970142580
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.997265604
Short name T820
Test name
Test status
Simulation time 41351092 ps
CPU time 0.94 seconds
Started Jul 09 05:03:57 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 198520 kb
Host smart-31256ab7-64f1-4999-b1e4-39e946607002
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997265604 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.997265604
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2276861610
Short name T65
Test name
Test status
Simulation time 15269514 ps
CPU time 0.61 seconds
Started Jul 09 05:03:59 PM PDT 24
Finished Jul 09 05:04:02 PM PDT 24
Peak memory 194928 kb
Host smart-6c3b23ec-3f74-4f81-ab4b-251f2016aa29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276861610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2276861610
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2217711567
Short name T838
Test name
Test status
Simulation time 15644395 ps
CPU time 0.58 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 194920 kb
Host smart-5cb693a0-22ff-4271-9716-dc54d3648611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217711567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2217711567
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2669384622
Short name T78
Test name
Test status
Simulation time 35109395 ps
CPU time 0.88 seconds
Started Jul 09 05:03:55 PM PDT 24
Finished Jul 09 05:03:59 PM PDT 24
Peak memory 197668 kb
Host smart-166255d1-e09e-4877-9756-b3cd98bce4f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669384622 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2669384622
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1137541702
Short name T763
Test name
Test status
Simulation time 243725768 ps
CPU time 2.13 seconds
Started Jul 09 05:03:59 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 198604 kb
Host smart-ff99ac0f-9331-4dcd-870e-f670ef333f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137541702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1137541702
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.315059711
Short name T764
Test name
Test status
Simulation time 160414957 ps
CPU time 1.16 seconds
Started Jul 09 05:03:58 PM PDT 24
Finished Jul 09 05:04:02 PM PDT 24
Peak memory 198684 kb
Host smart-9c9429f0-fa4d-4a89-a6b2-ab6f616c0880
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315059711 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.315059711
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.334623727
Short name T67
Test name
Test status
Simulation time 30355785 ps
CPU time 0.63 seconds
Started Jul 09 05:03:57 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 195556 kb
Host smart-c75020f5-6afb-4c3a-8f5c-98f708f54030
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334623727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.334623727
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3993275471
Short name T840
Test name
Test status
Simulation time 45446175 ps
CPU time 0.58 seconds
Started Jul 09 05:04:00 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 194172 kb
Host smart-fed01003-5511-4f5d-8f43-560b4e5dcc0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993275471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3993275471
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.918292799
Short name T817
Test name
Test status
Simulation time 62328172 ps
CPU time 0.64 seconds
Started Jul 09 05:03:59 PM PDT 24
Finished Jul 09 05:04:02 PM PDT 24
Peak memory 195308 kb
Host smart-07191c10-51a2-48d3-9e5b-945aa721e83a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918292799 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.918292799
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.167346761
Short name T756
Test name
Test status
Simulation time 34451746 ps
CPU time 1.76 seconds
Started Jul 09 05:03:56 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 198700 kb
Host smart-1241c64f-7926-4369-bbbd-d3799872bc1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167346761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.167346761
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2227140378
Short name T101
Test name
Test status
Simulation time 77053982 ps
CPU time 1.18 seconds
Started Jul 09 05:03:57 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 198724 kb
Host smart-c34d9904-8273-4a3f-9ba2-35752aaef6c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227140378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2227140378
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4199599282
Short name T793
Test name
Test status
Simulation time 30008073 ps
CPU time 0.79 seconds
Started Jul 09 05:03:57 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 198448 kb
Host smart-acf13a60-de9b-4053-acec-a75db8d577ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199599282 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.4199599282
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.524496358
Short name T63
Test name
Test status
Simulation time 23417061 ps
CPU time 0.64 seconds
Started Jul 09 05:03:56 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 196072 kb
Host smart-6a14c432-917a-4857-9661-3619220589b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524496358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.524496358
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1975089569
Short name T794
Test name
Test status
Simulation time 31091699 ps
CPU time 0.64 seconds
Started Jul 09 05:04:03 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 194256 kb
Host smart-63f2aeb8-fbef-4992-930c-3f0a567aadc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975089569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1975089569
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3347439562
Short name T69
Test name
Test status
Simulation time 106123288 ps
CPU time 0.77 seconds
Started Jul 09 05:03:56 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 196652 kb
Host smart-b6531f05-ccfc-41b5-909d-f4c254ffba99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347439562 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3347439562
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.52379758
Short name T730
Test name
Test status
Simulation time 96688345 ps
CPU time 2.58 seconds
Started Jul 09 05:04:03 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 198644 kb
Host smart-101b1a57-54e9-43fb-b7e4-d5f69ed3a73e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52379758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.52379758
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3055441739
Short name T805
Test name
Test status
Simulation time 105317996 ps
CPU time 1.17 seconds
Started Jul 09 05:03:55 PM PDT 24
Finished Jul 09 05:04:00 PM PDT 24
Peak memory 198004 kb
Host smart-6da7723f-0a15-4baf-b88b-1bb57c9c318f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055441739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3055441739
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2693504413
Short name T825
Test name
Test status
Simulation time 90016380 ps
CPU time 0.87 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 198484 kb
Host smart-67e3578c-0007-41a6-8fc3-1e01efe06289
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693504413 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2693504413
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3097190289
Short name T812
Test name
Test status
Simulation time 37407136 ps
CPU time 0.59 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 195768 kb
Host smart-7e5b122a-dc79-4a14-b6db-d3823f3315c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097190289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3097190289
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.4100573135
Short name T733
Test name
Test status
Simulation time 11880619 ps
CPU time 0.64 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 194280 kb
Host smart-ec7027b6-e64d-468b-b17c-89e606fd1767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100573135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.4100573135
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.964433191
Short name T85
Test name
Test status
Simulation time 21819051 ps
CPU time 0.67 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 196156 kb
Host smart-de8ed817-30a1-41bf-b14b-bf304e38b91e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964433191 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.964433191
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1600016510
Short name T790
Test name
Test status
Simulation time 572774930 ps
CPU time 2.92 seconds
Started Jul 09 05:03:59 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 198656 kb
Host smart-5042353d-be6a-42a4-911b-4ad16b010bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600016510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1600016510
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1401838033
Short name T37
Test name
Test status
Simulation time 80513309 ps
CPU time 1.21 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 198544 kb
Host smart-ffde1ec4-8c18-4ee2-b81e-92de9677c853
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401838033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1401838033
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3630519753
Short name T772
Test name
Test status
Simulation time 30365827 ps
CPU time 0.87 seconds
Started Jul 09 05:03:59 PM PDT 24
Finished Jul 09 05:04:02 PM PDT 24
Peak memory 198460 kb
Host smart-451d06af-1bff-495e-bc70-27da6d6c547f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630519753 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3630519753
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2952093760
Short name T835
Test name
Test status
Simulation time 29119481 ps
CPU time 0.68 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 196144 kb
Host smart-42c32ffd-6868-4d88-9520-75878e09e351
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952093760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2952093760
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1632558400
Short name T781
Test name
Test status
Simulation time 11355617 ps
CPU time 0.64 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 194224 kb
Host smart-ca74700a-0739-433e-bf44-01e6fccf1bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632558400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1632558400
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3435664990
Short name T79
Test name
Test status
Simulation time 18873140 ps
CPU time 0.83 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 196868 kb
Host smart-c27df284-e839-4373-a5b3-b10ed4a394a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435664990 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3435664990
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.735951909
Short name T807
Test name
Test status
Simulation time 51053183 ps
CPU time 2.48 seconds
Started Jul 09 05:04:03 PM PDT 24
Finished Jul 09 05:04:06 PM PDT 24
Peak memory 198620 kb
Host smart-d6d8fe99-452c-436f-bcd4-b112176f0440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735951909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.735951909
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1777006300
Short name T34
Test name
Test status
Simulation time 107367772 ps
CPU time 0.87 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 198488 kb
Host smart-cb390e9c-0cf3-4d3c-bd3d-156a5ee2cf6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777006300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1777006300
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3560514742
Short name T723
Test name
Test status
Simulation time 12611442 ps
CPU time 0.69 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 198476 kb
Host smart-0b638bd6-ee0d-4b87-8c31-4b5f3396097a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560514742 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3560514742
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3911101633
Short name T66
Test name
Test status
Simulation time 26614531 ps
CPU time 0.63 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 195968 kb
Host smart-7c8c0ea3-41f8-403e-ad25-444025a92899
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911101633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3911101633
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1921585493
Short name T749
Test name
Test status
Simulation time 32564604 ps
CPU time 0.59 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 194840 kb
Host smart-76842d3c-e556-4ac5-937f-ed7e47118237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921585493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1921585493
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1612810711
Short name T84
Test name
Test status
Simulation time 62471672 ps
CPU time 0.82 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 196740 kb
Host smart-9d9a21be-a71c-41a8-adf5-b85c1a2dc1ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612810711 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1612810711
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1010544823
Short name T834
Test name
Test status
Simulation time 74220386 ps
CPU time 1.86 seconds
Started Jul 09 05:04:00 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 198552 kb
Host smart-f99d33a1-f8e8-4580-bc83-7c152c513f81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010544823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1010544823
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2484657029
Short name T768
Test name
Test status
Simulation time 41027138 ps
CPU time 0.91 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 197508 kb
Host smart-221c3215-2dd3-457d-bc56-42129b158c4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484657029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2484657029
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.617557729
Short name T846
Test name
Test status
Simulation time 156169310 ps
CPU time 0.69 seconds
Started Jul 09 05:03:48 PM PDT 24
Finished Jul 09 05:03:50 PM PDT 24
Peak memory 194788 kb
Host smart-a192e91c-856c-4ad5-82b8-7f44140dfeb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617557729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.617557729
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1959891394
Short name T831
Test name
Test status
Simulation time 204238107 ps
CPU time 2.15 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:53 PM PDT 24
Peak memory 197516 kb
Host smart-b4e1038d-a4dc-4a6a-8d59-ca8bd408235d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959891394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1959891394
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.342848122
Short name T824
Test name
Test status
Simulation time 17873046 ps
CPU time 0.69 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:50 PM PDT 24
Peak memory 195368 kb
Host smart-3113b6ed-d245-4581-9076-51374b3c311b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342848122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.342848122
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.393591307
Short name T741
Test name
Test status
Simulation time 31623359 ps
CPU time 0.76 seconds
Started Jul 09 05:04:00 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 198432 kb
Host smart-2754c375-8799-4eee-b0d8-a0cf02a3ff28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393591307 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.393591307
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.404485935
Short name T77
Test name
Test status
Simulation time 56348377 ps
CPU time 0.65 seconds
Started Jul 09 05:03:47 PM PDT 24
Finished Jul 09 05:03:49 PM PDT 24
Peak memory 196020 kb
Host smart-9800a98b-8567-4f2e-b9a7-b6f92a0ae88c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404485935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.404485935
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.830789169
Short name T750
Test name
Test status
Simulation time 12185262 ps
CPU time 0.63 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:52 PM PDT 24
Peak memory 195080 kb
Host smart-db6de7a3-9c08-4e99-9b7f-553791ba6ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830789169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.830789169
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3441976127
Short name T809
Test name
Test status
Simulation time 83812345 ps
CPU time 0.83 seconds
Started Jul 09 05:04:01 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 197528 kb
Host smart-45d7f96f-8c27-433c-a6f2-ec8fd9b2af0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441976127 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3441976127
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2102198663
Short name T757
Test name
Test status
Simulation time 71666742 ps
CPU time 2.07 seconds
Started Jul 09 05:03:55 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 198576 kb
Host smart-46816718-a01a-48b7-a2f1-65486a5ee230
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102198663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2102198663
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4105381781
Short name T783
Test name
Test status
Simulation time 87907227 ps
CPU time 1.21 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 198700 kb
Host smart-5f37bb6f-ddee-4248-aa16-83d6213a7181
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105381781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4105381781
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3785612303
Short name T795
Test name
Test status
Simulation time 30090623 ps
CPU time 0.61 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 194228 kb
Host smart-7bf0263e-1cd4-4257-89cf-5888ae387256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785612303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3785612303
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1013522569
Short name T784
Test name
Test status
Simulation time 63026316 ps
CPU time 0.63 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 194392 kb
Host smart-9b153bcd-d41a-41ec-b66b-b38922f5f456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013522569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1013522569
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.770816745
Short name T774
Test name
Test status
Simulation time 44338536 ps
CPU time 0.61 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:08 PM PDT 24
Peak memory 194324 kb
Host smart-d0586a09-0f59-4341-ab8a-59c09ec268e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770816745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.770816745
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2521980059
Short name T755
Test name
Test status
Simulation time 15481971 ps
CPU time 0.58 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 194292 kb
Host smart-6e44f864-87ad-4f70-8fb5-525e042362cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521980059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2521980059
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1126555966
Short name T737
Test name
Test status
Simulation time 13845287 ps
CPU time 0.65 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:06 PM PDT 24
Peak memory 194952 kb
Host smart-1bc6e1d1-5261-4dc2-a855-5dd95d05d153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126555966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1126555966
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2964224271
Short name T731
Test name
Test status
Simulation time 31018419 ps
CPU time 0.61 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:08 PM PDT 24
Peak memory 194952 kb
Host smart-ff05b4c0-0050-4a74-8c38-5a5b07428d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964224271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2964224271
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2551883418
Short name T782
Test name
Test status
Simulation time 57811966 ps
CPU time 0.64 seconds
Started Jul 09 05:04:04 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 194292 kb
Host smart-3608a28f-913f-454e-b4c5-06c6519a4caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551883418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2551883418
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.459910278
Short name T800
Test name
Test status
Simulation time 15369425 ps
CPU time 0.59 seconds
Started Jul 09 05:04:10 PM PDT 24
Finished Jul 09 05:04:12 PM PDT 24
Peak memory 194156 kb
Host smart-3000786f-563e-4acb-b51c-1c49a31d4324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459910278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.459910278
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4082794343
Short name T822
Test name
Test status
Simulation time 15344550 ps
CPU time 0.65 seconds
Started Jul 09 05:04:04 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 194448 kb
Host smart-6a00dfd7-da46-4ec3-9f80-ac7334c72f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082794343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4082794343
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3659578106
Short name T738
Test name
Test status
Simulation time 42555145 ps
CPU time 0.58 seconds
Started Jul 09 05:04:09 PM PDT 24
Finished Jul 09 05:04:11 PM PDT 24
Peak memory 194176 kb
Host smart-dfb7197e-ae93-4e2a-ba16-127346cb2aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659578106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3659578106
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3061966434
Short name T73
Test name
Test status
Simulation time 28716463 ps
CPU time 0.77 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 196216 kb
Host smart-bc214c18-741c-4afc-9d7a-abc0593864c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061966434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3061966434
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.454007205
Short name T787
Test name
Test status
Simulation time 257892418 ps
CPU time 1.38 seconds
Started Jul 09 05:03:48 PM PDT 24
Finished Jul 09 05:03:51 PM PDT 24
Peak memory 196392 kb
Host smart-624f9d2d-9595-43d9-87d4-0458e02ef8f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454007205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.454007205
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1275472613
Short name T64
Test name
Test status
Simulation time 131844263 ps
CPU time 0.64 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:53 PM PDT 24
Peak memory 195456 kb
Host smart-f1edf8a7-cb6f-4feb-a3aa-9bc42bbc1439
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275472613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1275472613
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1742547447
Short name T837
Test name
Test status
Simulation time 84494655 ps
CPU time 0.82 seconds
Started Jul 09 05:03:48 PM PDT 24
Finished Jul 09 05:03:49 PM PDT 24
Peak memory 198440 kb
Host smart-52049d99-4744-448b-aa39-f8bf65b9d00e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742547447 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1742547447
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2724534166
Short name T766
Test name
Test status
Simulation time 45742386 ps
CPU time 0.65 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 196072 kb
Host smart-f6915c77-77e5-42a9-a6de-e9a491a39a79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724534166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2724534166
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3520981764
Short name T802
Test name
Test status
Simulation time 10826837 ps
CPU time 0.6 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 194620 kb
Host smart-efefacc3-4761-4335-9070-d65273da1429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520981764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3520981764
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2246911916
Short name T780
Test name
Test status
Simulation time 61631405 ps
CPU time 0.85 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:53 PM PDT 24
Peak memory 196804 kb
Host smart-813371dc-c559-4fa6-b246-83a9724c5bd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246911916 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2246911916
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2914501506
Short name T801
Test name
Test status
Simulation time 196360651 ps
CPU time 1.63 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:53 PM PDT 24
Peak memory 198648 kb
Host smart-d3214aae-ffc1-4f12-a23a-e2c754dbb352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914501506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2914501506
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.661116689
Short name T100
Test name
Test status
Simulation time 230662074 ps
CPU time 1.41 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:53 PM PDT 24
Peak memory 198636 kb
Host smart-8f067e38-376d-42a1-84b8-c0ed2f8e01c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661116689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.661116689
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3146684685
Short name T751
Test name
Test status
Simulation time 12212204 ps
CPU time 0.63 seconds
Started Jul 09 05:04:02 PM PDT 24
Finished Jul 09 05:04:04 PM PDT 24
Peak memory 194244 kb
Host smart-4e6823ab-f25e-4a78-a359-323816b21d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146684685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3146684685
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1220403845
Short name T804
Test name
Test status
Simulation time 53010488 ps
CPU time 0.63 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:08 PM PDT 24
Peak memory 194212 kb
Host smart-a0c2986e-3bde-47c5-a5dd-3cc396dba26c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220403845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1220403845
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3518412575
Short name T726
Test name
Test status
Simulation time 18107711 ps
CPU time 0.58 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 194244 kb
Host smart-23cb72f3-c82f-49cf-8fe1-8445dd626f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518412575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3518412575
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1059461628
Short name T762
Test name
Test status
Simulation time 11368404 ps
CPU time 0.61 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:08 PM PDT 24
Peak memory 194248 kb
Host smart-b25c83d5-454c-4aea-bf32-16d95af0ea3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059461628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1059461628
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1657429810
Short name T843
Test name
Test status
Simulation time 38516994 ps
CPU time 0.63 seconds
Started Jul 09 05:04:08 PM PDT 24
Finished Jul 09 05:04:09 PM PDT 24
Peak memory 195016 kb
Host smart-bf6f825e-0992-40cf-9e47-94c8c608a70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657429810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1657429810
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.655294419
Short name T745
Test name
Test status
Simulation time 34967133 ps
CPU time 0.59 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 194192 kb
Host smart-6951a825-d1f5-409a-a7f1-8a5c8b0c6668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655294419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.655294419
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2199335407
Short name T796
Test name
Test status
Simulation time 37649348 ps
CPU time 0.62 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:06 PM PDT 24
Peak memory 194200 kb
Host smart-c3c5a504-4050-4a4c-a35b-3e48c131107a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199335407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2199335407
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3893498413
Short name T739
Test name
Test status
Simulation time 13797967 ps
CPU time 0.69 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 194876 kb
Host smart-379b9fe1-4ca3-4a3b-b86d-abdf6946e1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893498413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3893498413
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1028395728
Short name T754
Test name
Test status
Simulation time 80039815 ps
CPU time 0.62 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:06 PM PDT 24
Peak memory 194828 kb
Host smart-c66c7ce5-336c-47ee-ac51-0cddbcc92671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028395728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1028395728
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1951026260
Short name T761
Test name
Test status
Simulation time 14731246 ps
CPU time 0.66 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:08 PM PDT 24
Peak memory 194896 kb
Host smart-a779d21e-9975-4751-915c-da9856cfb430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951026260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1951026260
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3295434148
Short name T753
Test name
Test status
Simulation time 37161504 ps
CPU time 1.45 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:52 PM PDT 24
Peak memory 198568 kb
Host smart-af225101-05fb-49d5-93dd-fb341a541e73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295434148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3295434148
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3157087283
Short name T752
Test name
Test status
Simulation time 22645665 ps
CPU time 0.65 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:50 PM PDT 24
Peak memory 195940 kb
Host smart-231d3b09-6832-41df-9d0a-669ff82b26f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157087283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3157087283
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3170926922
Short name T743
Test name
Test status
Simulation time 117860414 ps
CPU time 0.99 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 198508 kb
Host smart-c72844d8-ef41-4a35-bfd1-745a2bbe2244
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170926922 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3170926922
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.367779074
Short name T70
Test name
Test status
Simulation time 122533189 ps
CPU time 0.62 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 195268 kb
Host smart-b6f99534-63c6-424e-9f84-043157fd46c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367779074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.367779074
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.811512051
Short name T740
Test name
Test status
Simulation time 68475162 ps
CPU time 0.63 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:53 PM PDT 24
Peak memory 194256 kb
Host smart-2a2d54bf-81b9-408e-b90d-e54edd8db3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811512051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.811512051
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2611425707
Short name T86
Test name
Test status
Simulation time 63197302 ps
CPU time 0.88 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:54 PM PDT 24
Peak memory 197288 kb
Host smart-7e13cc26-6ab3-4367-8455-03c507d77d71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611425707 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2611425707
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2173400921
Short name T773
Test name
Test status
Simulation time 267112835 ps
CPU time 3.74 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 198652 kb
Host smart-e2cb8b7b-85d0-434e-96fe-a8e393449457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173400921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2173400921
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3925047600
Short name T36
Test name
Test status
Simulation time 100172592 ps
CPU time 1.57 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:54 PM PDT 24
Peak memory 198684 kb
Host smart-9a09694e-c011-40b5-bb16-527e5e8f1c58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925047600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3925047600
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.4189545992
Short name T779
Test name
Test status
Simulation time 25283833 ps
CPU time 0.6 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:06 PM PDT 24
Peak memory 194240 kb
Host smart-249aef9d-b142-4052-9fe6-da6e8f1d8d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189545992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.4189545992
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1889643134
Short name T758
Test name
Test status
Simulation time 15316318 ps
CPU time 0.64 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:08 PM PDT 24
Peak memory 194236 kb
Host smart-f98b6841-4c36-4564-bc43-c4a02ac22f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889643134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1889643134
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.966867312
Short name T819
Test name
Test status
Simulation time 31507868 ps
CPU time 0.65 seconds
Started Jul 09 05:04:06 PM PDT 24
Finished Jul 09 05:04:08 PM PDT 24
Peak memory 194416 kb
Host smart-2c34a405-67bb-472c-9cb8-299e10595d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966867312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.966867312
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1061459158
Short name T788
Test name
Test status
Simulation time 44783457 ps
CPU time 0.58 seconds
Started Jul 09 05:04:03 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 194216 kb
Host smart-f53b985c-9fac-4763-ae53-b3c5577970db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061459158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1061459158
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3058698891
Short name T821
Test name
Test status
Simulation time 40660877 ps
CPU time 0.61 seconds
Started Jul 09 05:04:05 PM PDT 24
Finished Jul 09 05:04:07 PM PDT 24
Peak memory 194260 kb
Host smart-41954591-836f-4a54-a582-f111676b9542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058698891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3058698891
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3873316083
Short name T735
Test name
Test status
Simulation time 14448486 ps
CPU time 0.61 seconds
Started Jul 09 05:04:04 PM PDT 24
Finished Jul 09 05:04:06 PM PDT 24
Peak memory 194252 kb
Host smart-49b62989-17ec-44ec-a154-b09629533a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873316083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3873316083
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.863596912
Short name T813
Test name
Test status
Simulation time 14249944 ps
CPU time 0.59 seconds
Started Jul 09 05:04:03 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 194180 kb
Host smart-a1f583b3-fef0-431e-896f-e94ce9ed5a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863596912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.863596912
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1820038983
Short name T725
Test name
Test status
Simulation time 13527013 ps
CPU time 0.62 seconds
Started Jul 09 05:04:04 PM PDT 24
Finished Jul 09 05:04:05 PM PDT 24
Peak memory 194864 kb
Host smart-5cfbb766-60bf-4de7-828d-0f0739dbdc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820038983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1820038983
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2499555901
Short name T816
Test name
Test status
Simulation time 63213878 ps
CPU time 0.59 seconds
Started Jul 09 05:04:09 PM PDT 24
Finished Jul 09 05:04:10 PM PDT 24
Peak memory 194228 kb
Host smart-c7d3a373-8ac7-467d-8ab1-c4b678b83edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499555901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2499555901
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1784214476
Short name T832
Test name
Test status
Simulation time 17983944 ps
CPU time 0.61 seconds
Started Jul 09 05:04:08 PM PDT 24
Finished Jul 09 05:04:09 PM PDT 24
Peak memory 194952 kb
Host smart-882bf47c-3707-4799-9510-951effe6afe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784214476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1784214476
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2644637529
Short name T728
Test name
Test status
Simulation time 19047694 ps
CPU time 1 seconds
Started Jul 09 05:03:48 PM PDT 24
Finished Jul 09 05:03:49 PM PDT 24
Peak memory 198512 kb
Host smart-9a518ace-b4c2-4671-988d-26b5a74b0716
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644637529 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2644637529
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3948772191
Short name T830
Test name
Test status
Simulation time 52122686 ps
CPU time 0.61 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:52 PM PDT 24
Peak memory 195340 kb
Host smart-b1c7c490-4843-4cc5-bba0-ae55e1c39870
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948772191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3948772191
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3791763436
Short name T721
Test name
Test status
Simulation time 11763507 ps
CPU time 0.6 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 194316 kb
Host smart-eb8ee174-5b17-4d30-afbc-1e3f7b184b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791763436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3791763436
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2978895445
Short name T815
Test name
Test status
Simulation time 17317183 ps
CPU time 0.67 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:51 PM PDT 24
Peak memory 195460 kb
Host smart-b41b134a-4b32-4a50-b92d-9023ffb8e5fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978895445 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2978895445
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2294890428
Short name T791
Test name
Test status
Simulation time 143254187 ps
CPU time 1.18 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:51 PM PDT 24
Peak memory 198708 kb
Host smart-d09070d0-2690-4568-a0d4-28df9e76593f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294890428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2294890428
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3266953663
Short name T744
Test name
Test status
Simulation time 126660427 ps
CPU time 0.94 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 198516 kb
Host smart-088239c9-97d6-48b3-950a-d163f40e2305
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266953663 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3266953663
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1232793501
Short name T775
Test name
Test status
Simulation time 16200853 ps
CPU time 0.64 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 195920 kb
Host smart-73a316b4-eb02-4c60-b4b3-d2027f3960af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232793501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1232793501
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2953891721
Short name T814
Test name
Test status
Simulation time 53623677 ps
CPU time 0.58 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 194308 kb
Host smart-7ed6579a-7504-4b5e-92fe-30e5d5d9da70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953891721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2953891721
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4106775291
Short name T799
Test name
Test status
Simulation time 100801255 ps
CPU time 0.76 seconds
Started Jul 09 05:04:00 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 197392 kb
Host smart-9e750b02-89ce-47af-a8ff-ce3785b037eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106775291 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4106775291
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1354452215
Short name T823
Test name
Test status
Simulation time 1341874075 ps
CPU time 3.04 seconds
Started Jul 09 05:04:27 PM PDT 24
Finished Jul 09 05:04:31 PM PDT 24
Peak memory 198512 kb
Host smart-d5a25b4c-b145-46a8-97ad-8e238b81c5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354452215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1354452215
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3327317479
Short name T770
Test name
Test status
Simulation time 392225035 ps
CPU time 1.16 seconds
Started Jul 09 05:03:49 PM PDT 24
Finished Jul 09 05:03:52 PM PDT 24
Peak memory 198712 kb
Host smart-4f2d51b2-2890-4445-a0e4-9bb92ca124c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327317479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3327317479
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.26904580
Short name T811
Test name
Test status
Simulation time 30851220 ps
CPU time 0.73 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 198112 kb
Host smart-691459a2-a3cf-4799-8d3e-c3d3e07a3f62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26904580 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.26904580
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1134172641
Short name T75
Test name
Test status
Simulation time 11811776 ps
CPU time 0.68 seconds
Started Jul 09 05:03:51 PM PDT 24
Finished Jul 09 05:03:55 PM PDT 24
Peak memory 195520 kb
Host smart-09d4e81a-575b-487a-9310-d3c305954ba6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134172641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1134172641
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1120604060
Short name T833
Test name
Test status
Simulation time 58454822 ps
CPU time 0.63 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 194248 kb
Host smart-d28abb3d-0425-453d-bc78-bd87bbf2f6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120604060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1120604060
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.103780728
Short name T81
Test name
Test status
Simulation time 58796585 ps
CPU time 0.63 seconds
Started Jul 09 05:03:55 PM PDT 24
Finished Jul 09 05:03:59 PM PDT 24
Peak memory 194796 kb
Host smart-437069a8-fc6e-4b4d-9b13-39cd267b75b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103780728 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.103780728
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3330462073
Short name T760
Test name
Test status
Simulation time 197720566 ps
CPU time 2.93 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:59 PM PDT 24
Peak memory 198600 kb
Host smart-e2f20314-a3e6-4a2f-a64c-802c5cee9abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330462073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3330462073
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.596039192
Short name T25
Test name
Test status
Simulation time 322833823 ps
CPU time 1.19 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 198568 kb
Host smart-14384aa1-e7fd-4301-be15-2f6630612392
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596039192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.596039192
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2019733993
Short name T729
Test name
Test status
Simulation time 70210891 ps
CPU time 1.68 seconds
Started Jul 09 05:04:00 PM PDT 24
Finished Jul 09 05:04:03 PM PDT 24
Peak memory 195908 kb
Host smart-f9d279d2-096b-4a11-91f4-83c9d0aaaf5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019733993 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2019733993
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4052831353
Short name T72
Test name
Test status
Simulation time 22267546 ps
CPU time 0.61 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 194912 kb
Host smart-3a48f24a-df0b-49a1-b61b-675f64fc639d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052831353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.4052831353
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3639269410
Short name T786
Test name
Test status
Simulation time 45921859 ps
CPU time 0.62 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 194296 kb
Host smart-27badde0-e835-4956-85a3-6c740c471a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639269410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3639269410
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3117008081
Short name T765
Test name
Test status
Simulation time 120892481 ps
CPU time 0.89 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 196788 kb
Host smart-33a1ca15-7ec9-4eba-8177-3fac40b40847
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117008081 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3117008081
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3343434709
Short name T792
Test name
Test status
Simulation time 407273779 ps
CPU time 2.24 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 198612 kb
Host smart-ad7ddd40-aa75-4a0a-964b-e1da36af5435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343434709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3343434709
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.663808549
Short name T38
Test name
Test status
Simulation time 294486657 ps
CPU time 0.92 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 198412 kb
Host smart-ddc7108e-1e4a-4e2b-b7f5-d6050b4a662b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663808549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.663808549
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4156261489
Short name T818
Test name
Test status
Simulation time 30332863 ps
CPU time 0.95 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:59 PM PDT 24
Peak memory 198496 kb
Host smart-da293f9e-1aa4-4a0d-ba1c-59428e22a9d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156261489 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4156261489
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3534792607
Short name T68
Test name
Test status
Simulation time 21355296 ps
CPU time 0.63 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 195604 kb
Host smart-c19110ae-5b79-4d2c-b620-0906daa89e98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534792607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3534792607
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3397621667
Short name T789
Test name
Test status
Simulation time 16819065 ps
CPU time 0.66 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 194212 kb
Host smart-b941d889-f0e2-43d6-8ab7-81df54779b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397621667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3397621667
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2538983502
Short name T769
Test name
Test status
Simulation time 188760969 ps
CPU time 0.82 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 196788 kb
Host smart-92db62a6-c9dd-4872-9cb4-faacc49e8963
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538983502 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2538983502
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2696107446
Short name T778
Test name
Test status
Simulation time 138883102 ps
CPU time 1.95 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 198624 kb
Host smart-6115311b-64b3-4837-a9e4-5bf070e4a4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696107446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2696107446
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3261655381
Short name T836
Test name
Test status
Simulation time 57483187 ps
CPU time 0.84 seconds
Started Jul 09 05:03:52 PM PDT 24
Finished Jul 09 05:03:56 PM PDT 24
Peak memory 197632 kb
Host smart-1038624d-e732-488d-a4d6-c7e432e9da8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261655381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3261655381
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1169786354
Short name T585
Test name
Test status
Simulation time 30765895 ps
CPU time 0.55 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:46 PM PDT 24
Peak memory 194304 kb
Host smart-79af3535-2067-4e8c-92a5-65160a0af9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169786354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1169786354
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1236990060
Short name T534
Test name
Test status
Simulation time 41308981 ps
CPU time 0.76 seconds
Started Jul 09 04:37:34 PM PDT 24
Finished Jul 09 04:37:37 PM PDT 24
Peak memory 195876 kb
Host smart-3d3aba67-b48f-474d-ba1d-8eff9c6d1eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236990060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1236990060
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.127879998
Short name T387
Test name
Test status
Simulation time 536719715 ps
CPU time 11.99 seconds
Started Jul 09 04:37:34 PM PDT 24
Finished Jul 09 04:37:48 PM PDT 24
Peak memory 197372 kb
Host smart-7bd7f0b0-271d-4d49-ac1a-b94c9bc83a62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127879998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.127879998
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2981776329
Short name T546
Test name
Test status
Simulation time 67745655 ps
CPU time 0.92 seconds
Started Jul 09 04:37:36 PM PDT 24
Finished Jul 09 04:37:39 PM PDT 24
Peak memory 198360 kb
Host smart-367bff08-3b20-4357-8c77-ece300d4472c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981776329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2981776329
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2899505893
Short name T621
Test name
Test status
Simulation time 187297377 ps
CPU time 1.37 seconds
Started Jul 09 04:37:32 PM PDT 24
Finished Jul 09 04:37:35 PM PDT 24
Peak memory 198616 kb
Host smart-82e32036-4b09-42e7-9b31-d2a5f2d6f9ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899505893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2899505893
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.710590990
Short name T506
Test name
Test status
Simulation time 119855806 ps
CPU time 1.38 seconds
Started Jul 09 04:37:36 PM PDT 24
Finished Jul 09 04:37:40 PM PDT 24
Peak memory 197260 kb
Host smart-e098438b-f4d5-40d2-94af-7e6afc0adb2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710590990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.710590990
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1813110301
Short name T447
Test name
Test status
Simulation time 29041483 ps
CPU time 0.99 seconds
Started Jul 09 04:37:34 PM PDT 24
Finished Jul 09 04:37:37 PM PDT 24
Peak memory 196112 kb
Host smart-38e7f3e4-f1ca-43f6-af57-ef60235970a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813110301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1813110301
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3956519347
Short name T171
Test name
Test status
Simulation time 159088997 ps
CPU time 1.01 seconds
Started Jul 09 04:37:34 PM PDT 24
Finished Jul 09 04:37:37 PM PDT 24
Peak memory 196456 kb
Host smart-525a5ebc-87f8-4030-828a-3c9f71ba288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956519347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3956519347
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3142989843
Short name T558
Test name
Test status
Simulation time 78369214 ps
CPU time 1.09 seconds
Started Jul 09 04:37:33 PM PDT 24
Finished Jul 09 04:37:36 PM PDT 24
Peak memory 196640 kb
Host smart-0552813a-c269-4eba-829e-368549f21d26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142989843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3142989843
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2820368425
Short name T109
Test name
Test status
Simulation time 635595595 ps
CPU time 2.86 seconds
Started Jul 09 04:37:32 PM PDT 24
Finished Jul 09 04:37:37 PM PDT 24
Peak memory 198468 kb
Host smart-aba6dada-a11d-4b81-9916-9262617a7a9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820368425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2820368425
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3517215068
Short name T42
Test name
Test status
Simulation time 225828728 ps
CPU time 0.8 seconds
Started Jul 09 04:37:36 PM PDT 24
Finished Jul 09 04:37:39 PM PDT 24
Peak memory 214092 kb
Host smart-2c3701d9-65fd-4d4e-9a56-dec555b7b4fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517215068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3517215068
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3254132027
Short name T11
Test name
Test status
Simulation time 63269277 ps
CPU time 1.21 seconds
Started Jul 09 04:37:32 PM PDT 24
Finished Jul 09 04:37:36 PM PDT 24
Peak memory 196076 kb
Host smart-ab3a479f-7cd5-44b4-ba8d-d665be198223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254132027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3254132027
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3433952832
Short name T419
Test name
Test status
Simulation time 56447736 ps
CPU time 0.8 seconds
Started Jul 09 04:37:35 PM PDT 24
Finished Jul 09 04:37:38 PM PDT 24
Peak memory 195868 kb
Host smart-41302fde-e473-4938-a8a3-155daf2a40ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433952832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3433952832
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3271665654
Short name T229
Test name
Test status
Simulation time 3566104877 ps
CPU time 45.65 seconds
Started Jul 09 04:37:33 PM PDT 24
Finished Jul 09 04:38:20 PM PDT 24
Peak memory 198652 kb
Host smart-5a4ea6dc-77f1-4e89-af42-da049f4d0e07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271665654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3271665654
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1008381977
Short name T633
Test name
Test status
Simulation time 65999972852 ps
CPU time 1076.32 seconds
Started Jul 09 04:37:39 PM PDT 24
Finished Jul 09 04:55:36 PM PDT 24
Peak memory 198828 kb
Host smart-3092927e-3254-46d2-80e8-938316a56783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1008381977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1008381977
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3105239122
Short name T314
Test name
Test status
Simulation time 27525245 ps
CPU time 0.8 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:46 PM PDT 24
Peak memory 195832 kb
Host smart-f9793fca-7d2d-4a94-b782-b5e5b9dfd978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105239122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3105239122
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4160865959
Short name T453
Test name
Test status
Simulation time 190538737 ps
CPU time 3.31 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:49 PM PDT 24
Peak memory 196480 kb
Host smart-d613b200-3bde-43d1-9bf8-954ceba42df4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160865959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4160865959
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1730444674
Short name T284
Test name
Test status
Simulation time 85980845 ps
CPU time 1 seconds
Started Jul 09 04:37:36 PM PDT 24
Finished Jul 09 04:37:39 PM PDT 24
Peak memory 198472 kb
Host smart-0d0d9b0f-4c07-42dc-9127-1f37bad3c115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730444674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1730444674
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1467794477
Short name T434
Test name
Test status
Simulation time 31538901 ps
CPU time 0.84 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:47 PM PDT 24
Peak memory 196080 kb
Host smart-adb39727-0736-494e-8f3e-d257d9147a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467794477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1467794477
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.535050844
Short name T464
Test name
Test status
Simulation time 353577280 ps
CPU time 3.14 seconds
Started Jul 09 04:37:36 PM PDT 24
Finished Jul 09 04:37:41 PM PDT 24
Peak memory 198612 kb
Host smart-66194fa5-63dc-42b4-be3f-c461c0e83749
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535050844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.535050844
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1574173682
Short name T129
Test name
Test status
Simulation time 114815257 ps
CPU time 1.63 seconds
Started Jul 09 04:37:38 PM PDT 24
Finished Jul 09 04:37:41 PM PDT 24
Peak memory 196512 kb
Host smart-25757776-ec82-454a-a639-67238d820ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574173682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1574173682
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1816235900
Short name T620
Test name
Test status
Simulation time 76928732 ps
CPU time 0.84 seconds
Started Jul 09 04:37:36 PM PDT 24
Finished Jul 09 04:37:39 PM PDT 24
Peak memory 196640 kb
Host smart-447cb3d0-4092-4ee1-a998-3f74da5e4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816235900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1816235900
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3394573778
Short name T136
Test name
Test status
Simulation time 35580929 ps
CPU time 0.63 seconds
Started Jul 09 04:37:37 PM PDT 24
Finished Jul 09 04:37:39 PM PDT 24
Peak memory 194792 kb
Host smart-851034e8-3fc9-4b1e-acb5-75dd48fea0ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394573778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3394573778
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.340287630
Short name T442
Test name
Test status
Simulation time 531078077 ps
CPU time 6.1 seconds
Started Jul 09 04:37:35 PM PDT 24
Finished Jul 09 04:37:44 PM PDT 24
Peak memory 198608 kb
Host smart-37f646e9-e6d2-4c93-b8a7-626d11a02d8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340287630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.340287630
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.2525568618
Short name T138
Test name
Test status
Simulation time 31457991 ps
CPU time 0.91 seconds
Started Jul 09 04:37:38 PM PDT 24
Finished Jul 09 04:37:40 PM PDT 24
Peak memory 195896 kb
Host smart-0ac21987-e17e-4e5b-988b-bc40cfd3982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525568618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2525568618
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2874137347
Short name T443
Test name
Test status
Simulation time 259103010 ps
CPU time 1.44 seconds
Started Jul 09 04:37:37 PM PDT 24
Finished Jul 09 04:37:40 PM PDT 24
Peak memory 197260 kb
Host smart-5f347b3d-3c94-4bfa-8387-e1f2015fecbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874137347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2874137347
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.857956262
Short name T548
Test name
Test status
Simulation time 30366994397 ps
CPU time 196.1 seconds
Started Jul 09 04:37:36 PM PDT 24
Finished Jul 09 04:40:55 PM PDT 24
Peak memory 198668 kb
Host smart-6b774eeb-f1e7-4c00-9c8b-892389bf06d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857956262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.857956262
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2542016732
Short name T23
Test name
Test status
Simulation time 521673958518 ps
CPU time 1737.02 seconds
Started Jul 09 04:37:37 PM PDT 24
Finished Jul 09 05:06:36 PM PDT 24
Peak memory 198808 kb
Host smart-7a7d87a7-7993-485d-a91f-a808b405d89c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2542016732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2542016732
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.982348900
Short name T241
Test name
Test status
Simulation time 11606646 ps
CPU time 0.58 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 194528 kb
Host smart-7a4dc0aa-4276-4d97-b539-90eecd5bb863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982348900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.982348900
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.50763596
Short name T626
Test name
Test status
Simulation time 17900608 ps
CPU time 0.62 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:08 PM PDT 24
Peak memory 194632 kb
Host smart-4ced6131-0e1b-4ebd-ad49-6e6321465d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50763596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.50763596
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2962609379
Short name T151
Test name
Test status
Simulation time 637149132 ps
CPU time 11.98 seconds
Started Jul 09 04:38:09 PM PDT 24
Finished Jul 09 04:38:22 PM PDT 24
Peak memory 196004 kb
Host smart-813985e9-5803-4393-a774-66b128de5cff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962609379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2962609379
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2361071920
Short name T316
Test name
Test status
Simulation time 27323834 ps
CPU time 0.66 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 195308 kb
Host smart-9469d34b-d61c-4d31-bd2f-ea775e568d9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361071920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2361071920
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4092629551
Short name T590
Test name
Test status
Simulation time 91630295 ps
CPU time 0.91 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 197724 kb
Host smart-2a01e0df-797d-4b03-9723-2787d2de2893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092629551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4092629551
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3959159895
Short name T104
Test name
Test status
Simulation time 126555118 ps
CPU time 2.61 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:11 PM PDT 24
Peak memory 198284 kb
Host smart-8e703011-bee4-414c-9b2c-41bfc3a1deed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959159895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3959159895
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2927270239
Short name T195
Test name
Test status
Simulation time 281689725 ps
CPU time 2.66 seconds
Started Jul 09 04:38:09 PM PDT 24
Finished Jul 09 04:38:13 PM PDT 24
Peak memory 197696 kb
Host smart-c2eb0b93-7560-4da6-a9da-fb57a50cbd28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927270239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2927270239
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2822038014
Short name T651
Test name
Test status
Simulation time 101298707 ps
CPU time 1.12 seconds
Started Jul 09 04:38:09 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 197344 kb
Host smart-39a2a707-e8f7-424a-8c25-0c01e7499de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822038014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2822038014
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.155676656
Short name T230
Test name
Test status
Simulation time 286504343 ps
CPU time 1.38 seconds
Started Jul 09 04:38:02 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 197432 kb
Host smart-7c4c0877-7814-45e7-b090-460783da8022
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155676656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.155676656
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3989745903
Short name T588
Test name
Test status
Simulation time 55988015 ps
CPU time 1.28 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:11 PM PDT 24
Peak memory 198176 kb
Host smart-68437c9e-6d60-49d1-94be-8d04c995f9ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989745903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3989745903
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.531215644
Short name T194
Test name
Test status
Simulation time 203004507 ps
CPU time 1.22 seconds
Started Jul 09 04:38:03 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 198476 kb
Host smart-71f6f9fe-ec44-40e4-973a-1e9e5f004680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531215644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.531215644
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3292636620
Short name T135
Test name
Test status
Simulation time 41014085 ps
CPU time 1.13 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 196408 kb
Host smart-5847ff2e-a9e1-48a6-ad70-49c9c80c3938
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292636620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3292636620
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3389979697
Short name T402
Test name
Test status
Simulation time 74947071500 ps
CPU time 135.5 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:40:25 PM PDT 24
Peak memory 198704 kb
Host smart-8c301a9e-7ba1-43b0-9866-95ae693e740b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389979697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3389979697
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.272455050
Short name T262
Test name
Test status
Simulation time 60707141017 ps
CPU time 1064.9 seconds
Started Jul 09 04:38:06 PM PDT 24
Finished Jul 09 04:55:52 PM PDT 24
Peak memory 198784 kb
Host smart-1ea4c440-bbb0-4948-bbb8-5ae7dd98a1f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=272455050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.272455050
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2141476753
Short name T339
Test name
Test status
Simulation time 27453202 ps
CPU time 0.56 seconds
Started Jul 09 04:38:10 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 194532 kb
Host smart-c99be557-74de-4899-a044-d979ef7e997f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141476753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2141476753
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.296881859
Short name T430
Test name
Test status
Simulation time 33717481 ps
CPU time 0.73 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:10 PM PDT 24
Peak memory 196400 kb
Host smart-ac7ffc21-ec01-48ef-bc37-589774c20745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296881859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.296881859
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.848114406
Short name T568
Test name
Test status
Simulation time 375845723 ps
CPU time 5.53 seconds
Started Jul 09 04:38:12 PM PDT 24
Finished Jul 09 04:38:19 PM PDT 24
Peak memory 198536 kb
Host smart-8804e429-51c6-4a67-936a-c100d86d98c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848114406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.848114406
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1336545709
Short name T148
Test name
Test status
Simulation time 307796117 ps
CPU time 1.06 seconds
Started Jul 09 04:38:11 PM PDT 24
Finished Jul 09 04:38:13 PM PDT 24
Peak memory 197176 kb
Host smart-2acd667b-cd81-49ec-98da-51f85c2deb2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336545709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1336545709
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2012023737
Short name T386
Test name
Test status
Simulation time 52128254 ps
CPU time 1.08 seconds
Started Jul 09 04:38:06 PM PDT 24
Finished Jul 09 04:38:08 PM PDT 24
Peak memory 196548 kb
Host smart-d3306cb5-a3b9-4c40-80f5-356b9586df09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012023737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2012023737
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4020487192
Short name T319
Test name
Test status
Simulation time 114119230 ps
CPU time 2.23 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:10 PM PDT 24
Peak memory 196840 kb
Host smart-291ae510-744b-4d50-900b-636cb8b7fe56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020487192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4020487192
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3599910306
Short name T408
Test name
Test status
Simulation time 259761376 ps
CPU time 1.67 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:11 PM PDT 24
Peak memory 196368 kb
Host smart-a3126db3-2bd9-4b61-984a-713daa9842f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599910306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3599910306
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.372367288
Short name T644
Test name
Test status
Simulation time 25789589 ps
CPU time 0.78 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:10 PM PDT 24
Peak memory 196688 kb
Host smart-74fd79bd-7c5b-4d68-bdc5-62433439d801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372367288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.372367288
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3664993509
Short name T573
Test name
Test status
Simulation time 33289525 ps
CPU time 1.15 seconds
Started Jul 09 04:38:09 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 197504 kb
Host smart-b4a51025-07c4-46b8-8f42-b537380521c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664993509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3664993509
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1816130061
Short name T605
Test name
Test status
Simulation time 332609505 ps
CPU time 5.29 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:15 PM PDT 24
Peak memory 198512 kb
Host smart-c5489d02-e5b9-4be4-969c-bc12899f4f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816130061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1816130061
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2174760335
Short name T631
Test name
Test status
Simulation time 488508913 ps
CPU time 0.85 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:10 PM PDT 24
Peak memory 196952 kb
Host smart-87352bc1-0bf4-4cbd-9605-bcd1ac3965f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174760335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2174760335
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2429309187
Short name T436
Test name
Test status
Simulation time 143040527 ps
CPU time 1.21 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 197648 kb
Host smart-ed78d159-f4d7-4b49-8782-985c1882a5f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429309187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2429309187
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.586018962
Short name T226
Test name
Test status
Simulation time 76857826147 ps
CPU time 186.31 seconds
Started Jul 09 04:38:09 PM PDT 24
Finished Jul 09 04:41:17 PM PDT 24
Peak memory 198640 kb
Host smart-ba78c40b-5895-4ce5-9a1f-1c73a3136aa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586018962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.586018962
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4104902916
Short name T576
Test name
Test status
Simulation time 60933075388 ps
CPU time 1196.66 seconds
Started Jul 09 04:38:13 PM PDT 24
Finished Jul 09 04:58:10 PM PDT 24
Peak memory 198700 kb
Host smart-eeb2590c-d2ac-4a79-9248-d4197531327c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4104902916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4104902916
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1510055260
Short name T538
Test name
Test status
Simulation time 60376434 ps
CPU time 0.55 seconds
Started Jul 09 04:38:13 PM PDT 24
Finished Jul 09 04:38:14 PM PDT 24
Peak memory 194840 kb
Host smart-f17ab7e7-f96c-4706-8722-634a2d06ae0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510055260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1510055260
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2604449262
Short name T250
Test name
Test status
Simulation time 88300646 ps
CPU time 0.68 seconds
Started Jul 09 04:38:14 PM PDT 24
Finished Jul 09 04:38:15 PM PDT 24
Peak memory 195676 kb
Host smart-88077d24-6c68-45fb-8323-319d970f566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604449262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2604449262
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.212297488
Short name T317
Test name
Test status
Simulation time 6714952645 ps
CPU time 20.94 seconds
Started Jul 09 04:38:12 PM PDT 24
Finished Jul 09 04:38:34 PM PDT 24
Peak memory 196544 kb
Host smart-f1ca1dcc-2c7c-4890-82db-0fa9ac847d35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212297488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.212297488
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2174854488
Short name T619
Test name
Test status
Simulation time 166055096 ps
CPU time 0.85 seconds
Started Jul 09 04:38:11 PM PDT 24
Finished Jul 09 04:38:13 PM PDT 24
Peak memory 196428 kb
Host smart-5a57224e-6f7e-49da-842d-789dacb50e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174854488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2174854488
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1032350578
Short name T437
Test name
Test status
Simulation time 396485068 ps
CPU time 1.06 seconds
Started Jul 09 04:38:12 PM PDT 24
Finished Jul 09 04:38:14 PM PDT 24
Peak memory 196624 kb
Host smart-fabfb665-ddc4-4fb3-b59a-f0d42541cf1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032350578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1032350578
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3512255666
Short name T507
Test name
Test status
Simulation time 42422942 ps
CPU time 0.93 seconds
Started Jul 09 04:38:12 PM PDT 24
Finished Jul 09 04:38:14 PM PDT 24
Peak memory 196724 kb
Host smart-324590bf-8af3-4872-89da-620589d80a14
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512255666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3512255666
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2030890965
Short name T486
Test name
Test status
Simulation time 83656793 ps
CPU time 1.77 seconds
Started Jul 09 04:38:11 PM PDT 24
Finished Jul 09 04:38:14 PM PDT 24
Peak memory 197216 kb
Host smart-4973a3c9-0175-4bfb-8041-915e0262f8c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030890965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2030890965
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.440682034
Short name T279
Test name
Test status
Simulation time 38566845 ps
CPU time 0.85 seconds
Started Jul 09 04:38:12 PM PDT 24
Finished Jul 09 04:38:14 PM PDT 24
Peak memory 197028 kb
Host smart-899f8fcd-b4e3-4de9-ae00-32f3bbfb2b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440682034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.440682034
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3457982116
Short name T603
Test name
Test status
Simulation time 183339235 ps
CPU time 1.19 seconds
Started Jul 09 04:38:15 PM PDT 24
Finished Jul 09 04:38:17 PM PDT 24
Peak memory 197708 kb
Host smart-21900937-a902-42f1-96f4-1bcad5d5a762
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457982116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3457982116
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.625656768
Short name T111
Test name
Test status
Simulation time 1039651775 ps
CPU time 3.2 seconds
Started Jul 09 04:38:15 PM PDT 24
Finished Jul 09 04:38:19 PM PDT 24
Peak memory 198548 kb
Host smart-a0f06158-ffab-4a9c-8902-3b441f3aba03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625656768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.625656768
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.854241381
Short name T168
Test name
Test status
Simulation time 185923036 ps
CPU time 1.17 seconds
Started Jul 09 04:38:10 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 198512 kb
Host smart-2051d012-28c4-48ee-86e9-0b04b38cb436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854241381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.854241381
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.178370945
Short name T180
Test name
Test status
Simulation time 261250925 ps
CPU time 1.34 seconds
Started Jul 09 04:38:14 PM PDT 24
Finished Jul 09 04:38:16 PM PDT 24
Peak memory 197360 kb
Host smart-359b826b-75a3-481e-a09f-6530174434d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178370945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.178370945
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1397572357
Short name T653
Test name
Test status
Simulation time 45357389105 ps
CPU time 154.1 seconds
Started Jul 09 04:38:10 PM PDT 24
Finished Jul 09 04:40:46 PM PDT 24
Peak memory 198612 kb
Host smart-8adc04f6-2b4a-4e36-8f1b-23fa175bccb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397572357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1397572357
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3340809168
Short name T55
Test name
Test status
Simulation time 633381082878 ps
CPU time 2193.77 seconds
Started Jul 09 04:38:10 PM PDT 24
Finished Jul 09 05:14:45 PM PDT 24
Peak memory 198816 kb
Host smart-c43126f1-2d20-434c-b724-b6d2d2a76c45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3340809168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3340809168
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3988468202
Short name T181
Test name
Test status
Simulation time 15327219 ps
CPU time 0.58 seconds
Started Jul 09 04:38:15 PM PDT 24
Finished Jul 09 04:38:16 PM PDT 24
Peak memory 194536 kb
Host smart-e418843b-3804-4b42-b1f5-455bbe9d811a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988468202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3988468202
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1862087187
Short name T710
Test name
Test status
Simulation time 121157214 ps
CPU time 0.66 seconds
Started Jul 09 04:38:17 PM PDT 24
Finished Jul 09 04:38:18 PM PDT 24
Peak memory 195320 kb
Host smart-81e7aef3-544f-4cac-ae18-c8e6e0b07fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862087187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1862087187
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.674474035
Short name T213
Test name
Test status
Simulation time 884612904 ps
CPU time 14.77 seconds
Started Jul 09 04:38:17 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 196096 kb
Host smart-a45da339-a35d-4e78-aa74-a3ea85586042
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674474035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.674474035
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3543833193
Short name T389
Test name
Test status
Simulation time 134377008 ps
CPU time 1.04 seconds
Started Jul 09 04:38:15 PM PDT 24
Finished Jul 09 04:38:17 PM PDT 24
Peak memory 196968 kb
Host smart-badd61f5-ee8e-4031-8ce6-c473a65945cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543833193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3543833193
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2998831731
Short name T569
Test name
Test status
Simulation time 269799104 ps
CPU time 1.09 seconds
Started Jul 09 04:38:14 PM PDT 24
Finished Jul 09 04:38:16 PM PDT 24
Peak memory 196640 kb
Host smart-e869d7e4-9fae-4bac-8705-e2413e30d260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998831731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2998831731
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.598935883
Short name T714
Test name
Test status
Simulation time 83845539 ps
CPU time 2.1 seconds
Started Jul 09 04:38:18 PM PDT 24
Finished Jul 09 04:38:21 PM PDT 24
Peak memory 198588 kb
Host smart-c8235761-2e4c-4e11-8134-d1dca42c3360
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598935883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.598935883
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2112193731
Short name T595
Test name
Test status
Simulation time 663303139 ps
CPU time 3.03 seconds
Started Jul 09 04:38:15 PM PDT 24
Finished Jul 09 04:38:18 PM PDT 24
Peak memory 197284 kb
Host smart-247ce505-9d36-4b1a-9e3e-92f5dcf38e51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112193731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2112193731
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2298167727
Short name T318
Test name
Test status
Simulation time 62833583 ps
CPU time 1.16 seconds
Started Jul 09 04:38:17 PM PDT 24
Finished Jul 09 04:38:18 PM PDT 24
Peak memory 196644 kb
Host smart-7037c54f-ed50-4d3a-b2a6-770896a81c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298167727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2298167727
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2390918603
Short name T694
Test name
Test status
Simulation time 50418065 ps
CPU time 0.63 seconds
Started Jul 09 04:38:18 PM PDT 24
Finished Jul 09 04:38:19 PM PDT 24
Peak memory 195480 kb
Host smart-4e03c87e-4dd2-43b5-8e33-9e090bdf086e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390918603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2390918603
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3286773822
Short name T561
Test name
Test status
Simulation time 182313622 ps
CPU time 4.34 seconds
Started Jul 09 04:38:16 PM PDT 24
Finished Jul 09 04:38:21 PM PDT 24
Peak memory 198432 kb
Host smart-bdc7d081-3961-4d49-ac7f-617e2007ae21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286773822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3286773822
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3327764314
Short name T367
Test name
Test status
Simulation time 37939533 ps
CPU time 0.88 seconds
Started Jul 09 04:38:10 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 196980 kb
Host smart-07d38c99-4faf-401c-afb2-94935160ed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327764314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3327764314
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2527689827
Short name T112
Test name
Test status
Simulation time 25845713 ps
CPU time 0.87 seconds
Started Jul 09 04:38:16 PM PDT 24
Finished Jul 09 04:38:18 PM PDT 24
Peak memory 196976 kb
Host smart-7524bffe-21e0-4c6b-a7cd-d61e8d7ee138
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527689827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2527689827
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1402945823
Short name T286
Test name
Test status
Simulation time 4171857969 ps
CPU time 102.8 seconds
Started Jul 09 04:38:17 PM PDT 24
Finished Jul 09 04:40:01 PM PDT 24
Peak memory 198576 kb
Host smart-9d092052-19ab-45f5-a989-c923ba431a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402945823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1402945823
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2963176757
Short name T485
Test name
Test status
Simulation time 59325327649 ps
CPU time 809.75 seconds
Started Jul 09 04:38:17 PM PDT 24
Finished Jul 09 04:51:48 PM PDT 24
Peak memory 198688 kb
Host smart-43cf9fba-a01d-4577-8756-c33371a992d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2963176757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2963176757
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.4128959216
Short name T33
Test name
Test status
Simulation time 27344048 ps
CPU time 0.57 seconds
Started Jul 09 04:38:22 PM PDT 24
Finished Jul 09 04:38:23 PM PDT 24
Peak memory 194760 kb
Host smart-771f7558-cf14-409e-b760-3f1ebcf9734a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128959216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4128959216
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3029410906
Short name T622
Test name
Test status
Simulation time 14561950 ps
CPU time 0.63 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:22 PM PDT 24
Peak memory 194564 kb
Host smart-9f206146-f65c-4faf-ab63-61b9003c7e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029410906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3029410906
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.4275518934
Short name T258
Test name
Test status
Simulation time 299907334 ps
CPU time 4.22 seconds
Started Jul 09 04:38:20 PM PDT 24
Finished Jul 09 04:38:24 PM PDT 24
Peak memory 196096 kb
Host smart-4a73f1cf-dafb-4ce4-bb03-afefcf44ca96
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275518934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.4275518934
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2993365147
Short name T6
Test name
Test status
Simulation time 52971577 ps
CPU time 0.7 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:24 PM PDT 24
Peak memory 195364 kb
Host smart-f93bd891-ccf1-46cb-a3aa-40c58645c183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993365147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2993365147
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2103984270
Short name T475
Test name
Test status
Simulation time 239440834 ps
CPU time 1.09 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:23 PM PDT 24
Peak memory 196352 kb
Host smart-0ba48b72-76c6-4e4f-b7dc-b1086aa26a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103984270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2103984270
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3519631614
Short name T705
Test name
Test status
Simulation time 73080583 ps
CPU time 1.37 seconds
Started Jul 09 04:38:19 PM PDT 24
Finished Jul 09 04:38:21 PM PDT 24
Peak memory 197112 kb
Host smart-548c06f1-ef88-4ab1-8f5b-8ff069dd22af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519631614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3519631614
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.31685565
Short name T454
Test name
Test status
Simulation time 152028615 ps
CPU time 2.97 seconds
Started Jul 09 04:38:20 PM PDT 24
Finished Jul 09 04:38:24 PM PDT 24
Peak memory 197804 kb
Host smart-0ab13b4b-0654-486d-aeb9-24b487e61d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31685565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.31685565
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1864220959
Short name T531
Test name
Test status
Simulation time 220005621 ps
CPU time 1.2 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:22 PM PDT 24
Peak memory 196508 kb
Host smart-1fec8d23-c7eb-4c51-a0f5-49db171e2c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864220959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1864220959
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4245234534
Short name T652
Test name
Test status
Simulation time 63706539 ps
CPU time 1.2 seconds
Started Jul 09 04:38:19 PM PDT 24
Finished Jul 09 04:38:21 PM PDT 24
Peak memory 198692 kb
Host smart-a54c1f5e-06e8-4d55-8ff9-8af09ffeea05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245234534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4245234534
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2233272403
Short name T413
Test name
Test status
Simulation time 361376894 ps
CPU time 6.23 seconds
Started Jul 09 04:38:20 PM PDT 24
Finished Jul 09 04:38:27 PM PDT 24
Peak memory 198304 kb
Host smart-000ecd5e-b002-46b2-9bfc-68236b0c6fd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233272403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2233272403
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1446844295
Short name T157
Test name
Test status
Simulation time 121799469 ps
CPU time 0.94 seconds
Started Jul 09 04:38:17 PM PDT 24
Finished Jul 09 04:38:19 PM PDT 24
Peak memory 197876 kb
Host smart-aea303d5-59d6-492c-82d3-c2c7450fa7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446844295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1446844295
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3469055006
Short name T337
Test name
Test status
Simulation time 74646255 ps
CPU time 1.35 seconds
Started Jul 09 04:38:20 PM PDT 24
Finished Jul 09 04:38:22 PM PDT 24
Peak memory 197648 kb
Host smart-6da6d4dd-a4d8-488b-acff-963a2743ef59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469055006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3469055006
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.4274967122
Short name T505
Test name
Test status
Simulation time 66134740955 ps
CPU time 160.84 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:41:02 PM PDT 24
Peak memory 198612 kb
Host smart-2b0f1d61-1e27-4f7d-a43c-2a01bd0fa604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274967122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.4274967122
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.410623778
Short name T608
Test name
Test status
Simulation time 219743494694 ps
CPU time 1875.99 seconds
Started Jul 09 04:38:18 PM PDT 24
Finished Jul 09 05:09:35 PM PDT 24
Peak memory 198784 kb
Host smart-498af414-6da4-4647-af98-e7dee978da4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=410623778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.410623778
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2149230100
Short name T92
Test name
Test status
Simulation time 10925382 ps
CPU time 0.57 seconds
Started Jul 09 04:38:24 PM PDT 24
Finished Jul 09 04:38:25 PM PDT 24
Peak memory 194368 kb
Host smart-462a6063-19f9-4343-9de2-60637ec9a5a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149230100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2149230100
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2315425761
Short name T554
Test name
Test status
Simulation time 50517850 ps
CPU time 0.97 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:23 PM PDT 24
Peak memory 196420 kb
Host smart-ea6ebae9-fa0a-4048-afc5-c9f411937e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315425761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2315425761
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3063338189
Short name T184
Test name
Test status
Simulation time 329502480 ps
CPU time 16.15 seconds
Started Jul 09 04:38:20 PM PDT 24
Finished Jul 09 04:38:37 PM PDT 24
Peak memory 197532 kb
Host smart-e456dc6c-62b5-4443-b51b-8452bf9cdcc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063338189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3063338189
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2224413610
Short name T209
Test name
Test status
Simulation time 303118720 ps
CPU time 0.77 seconds
Started Jul 09 04:38:18 PM PDT 24
Finished Jul 09 04:38:20 PM PDT 24
Peak memory 196328 kb
Host smart-2272b543-4c81-4875-ae9d-b22b5c838ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224413610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2224413610
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1187632393
Short name T175
Test name
Test status
Simulation time 25794894 ps
CPU time 0.85 seconds
Started Jul 09 04:38:24 PM PDT 24
Finished Jul 09 04:38:26 PM PDT 24
Peak memory 196060 kb
Host smart-25623f96-56c6-40af-adbf-548b6152ee7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187632393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1187632393
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1356095890
Short name T425
Test name
Test status
Simulation time 418995850 ps
CPU time 3.76 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:26 PM PDT 24
Peak memory 197696 kb
Host smart-d7706981-636c-4772-95ec-b511da690382
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356095890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1356095890
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.439802381
Short name T236
Test name
Test status
Simulation time 218691976 ps
CPU time 1.3 seconds
Started Jul 09 04:38:19 PM PDT 24
Finished Jul 09 04:38:21 PM PDT 24
Peak memory 197520 kb
Host smart-0c91144c-5ade-4360-b78e-9127871921ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439802381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
439802381
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.172874290
Short name T578
Test name
Test status
Simulation time 246280971 ps
CPU time 1.29 seconds
Started Jul 09 04:38:19 PM PDT 24
Finished Jul 09 04:38:20 PM PDT 24
Peak memory 197128 kb
Host smart-68ebf43a-3da5-451e-bf34-b00748cc788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172874290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.172874290
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3991717509
Short name T110
Test name
Test status
Simulation time 115831454 ps
CPU time 1.04 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:25 PM PDT 24
Peak memory 197196 kb
Host smart-67f99599-6c1e-4cd4-bfb7-71f1baafd768
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991717509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3991717509
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4018587525
Short name T373
Test name
Test status
Simulation time 1132373025 ps
CPU time 4.09 seconds
Started Jul 09 04:38:22 PM PDT 24
Finished Jul 09 04:38:27 PM PDT 24
Peak memory 198620 kb
Host smart-532dbd03-b959-4187-96b3-4fd1c55efde1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018587525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.4018587525
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3069892486
Short name T95
Test name
Test status
Simulation time 84154975 ps
CPU time 1.37 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:23 PM PDT 24
Peak memory 198524 kb
Host smart-c4fa0eb9-9c51-4df6-b785-208926195884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069892486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3069892486
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3357409862
Short name T632
Test name
Test status
Simulation time 151994988 ps
CPU time 1.03 seconds
Started Jul 09 04:38:20 PM PDT 24
Finished Jul 09 04:38:22 PM PDT 24
Peak memory 196376 kb
Host smart-d6ff20e5-e820-4022-ae77-6b427300ed08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357409862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3357409862
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4290645542
Short name T308
Test name
Test status
Simulation time 1599437423 ps
CPU time 27.04 seconds
Started Jul 09 04:38:20 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 198620 kb
Host smart-47b37755-1f5a-4e3b-9801-b484ca501681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290645542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4290645542
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1872421959
Short name T567
Test name
Test status
Simulation time 46043057 ps
CPU time 0.56 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:24 PM PDT 24
Peak memory 194708 kb
Host smart-c9ddcd5e-f38d-4a17-93f7-211462859079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872421959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1872421959
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1386080621
Short name T646
Test name
Test status
Simulation time 21769207 ps
CPU time 0.71 seconds
Started Jul 09 04:38:22 PM PDT 24
Finished Jul 09 04:38:23 PM PDT 24
Peak memory 195824 kb
Host smart-29e60f1a-44c1-4c44-bb56-e56969a6c350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386080621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1386080621
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1778187021
Short name T599
Test name
Test status
Simulation time 875724629 ps
CPU time 26.82 seconds
Started Jul 09 04:38:22 PM PDT 24
Finished Jul 09 04:38:50 PM PDT 24
Peak memory 197368 kb
Host smart-1a6b8b2b-0d76-43c5-ba9b-99d6d6e12c03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778187021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1778187021
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1156905816
Short name T659
Test name
Test status
Simulation time 48371850 ps
CPU time 0.69 seconds
Started Jul 09 04:38:27 PM PDT 24
Finished Jul 09 04:38:28 PM PDT 24
Peak memory 195176 kb
Host smart-9db2c2b2-e8e6-4499-a27e-b4bf8a118955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156905816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1156905816
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3040106964
Short name T88
Test name
Test status
Simulation time 261051302 ps
CPU time 1.02 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:23 PM PDT 24
Peak memory 196512 kb
Host smart-904bc713-c581-42a1-aacd-d70646d893ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040106964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3040106964
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2158939481
Short name T324
Test name
Test status
Simulation time 78865248 ps
CPU time 3.04 seconds
Started Jul 09 04:38:24 PM PDT 24
Finished Jul 09 04:38:27 PM PDT 24
Peak memory 198700 kb
Host smart-ba58b319-9faa-4124-8aa0-87ad086e85a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158939481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2158939481
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.935273505
Short name T643
Test name
Test status
Simulation time 301679407 ps
CPU time 2.43 seconds
Started Jul 09 04:38:26 PM PDT 24
Finished Jul 09 04:38:30 PM PDT 24
Peak memory 197664 kb
Host smart-fbaddb30-e4e8-4974-96f8-3d6f557674bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935273505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
935273505
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.897891282
Short name T624
Test name
Test status
Simulation time 281436426 ps
CPU time 1.41 seconds
Started Jul 09 04:38:25 PM PDT 24
Finished Jul 09 04:38:27 PM PDT 24
Peak memory 196408 kb
Host smart-818031f3-a271-4199-b4df-918b18a015ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897891282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.897891282
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3321762901
Short name T366
Test name
Test status
Simulation time 1384356506 ps
CPU time 1.25 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:25 PM PDT 24
Peak memory 197552 kb
Host smart-1f8c2daa-cb35-4995-817b-e57910cc8e1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321762901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3321762901
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2588816746
Short name T719
Test name
Test status
Simulation time 293164591 ps
CPU time 3.57 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:28 PM PDT 24
Peak memory 198008 kb
Host smart-a9fb3cbe-9e52-4e72-8f06-50fb2834c402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588816746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2588816746
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.610445103
Short name T301
Test name
Test status
Simulation time 94931370 ps
CPU time 1.44 seconds
Started Jul 09 04:38:24 PM PDT 24
Finished Jul 09 04:38:26 PM PDT 24
Peak memory 197344 kb
Host smart-cc6fc4fc-7a5b-43d3-9ee4-1a39cdb6d050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610445103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.610445103
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3423305045
Short name T166
Test name
Test status
Simulation time 54635458 ps
CPU time 1.1 seconds
Started Jul 09 04:38:21 PM PDT 24
Finished Jul 09 04:38:23 PM PDT 24
Peak memory 197044 kb
Host smart-ca6a1688-2e13-49c1-8adc-7731e3e6b66f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423305045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3423305045
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.4021153537
Short name T701
Test name
Test status
Simulation time 15254165093 ps
CPU time 27.58 seconds
Started Jul 09 04:38:29 PM PDT 24
Finished Jul 09 04:38:58 PM PDT 24
Peak memory 198540 kb
Host smart-8a91aaaf-b827-4891-9d5f-032fbf2ff1cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021153537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.4021153537
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.277680565
Short name T57
Test name
Test status
Simulation time 508512801539 ps
CPU time 2139.03 seconds
Started Jul 09 04:38:24 PM PDT 24
Finished Jul 09 05:14:03 PM PDT 24
Peak memory 198892 kb
Host smart-fe249aa8-7965-4e06-a842-2eeda48e34a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=277680565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.277680565
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1126290608
Short name T145
Test name
Test status
Simulation time 77260390 ps
CPU time 0.57 seconds
Started Jul 09 04:38:28 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 195436 kb
Host smart-16128b1b-9b23-4415-9e3b-e7df26540753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126290608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1126290608
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.726057888
Short name T405
Test name
Test status
Simulation time 211408722 ps
CPU time 0.82 seconds
Started Jul 09 04:38:26 PM PDT 24
Finished Jul 09 04:38:28 PM PDT 24
Peak memory 196540 kb
Host smart-09771943-4930-41b4-ade5-e4efc4d579cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726057888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.726057888
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2673874672
Short name T565
Test name
Test status
Simulation time 166568131 ps
CPU time 7.69 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:32 PM PDT 24
Peak memory 197504 kb
Host smart-d5295147-6b7e-481c-a044-c62c021eb366
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673874672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2673874672
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4005986667
Short name T514
Test name
Test status
Simulation time 28367595 ps
CPU time 0.71 seconds
Started Jul 09 04:38:30 PM PDT 24
Finished Jul 09 04:38:32 PM PDT 24
Peak memory 195292 kb
Host smart-e0009258-613e-4de8-a429-103b86c10597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005986667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4005986667
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.487399392
Short name T352
Test name
Test status
Simulation time 237285148 ps
CPU time 1.07 seconds
Started Jul 09 04:38:25 PM PDT 24
Finished Jul 09 04:38:26 PM PDT 24
Peak memory 196436 kb
Host smart-2c0d8888-93da-4560-871f-685f6d2b56bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487399392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.487399392
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.4087961758
Short name T323
Test name
Test status
Simulation time 272762682 ps
CPU time 2.63 seconds
Started Jul 09 04:38:26 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 198508 kb
Host smart-041b8216-0f38-40f7-bb35-926f33f4b5d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087961758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.4087961758
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2323725936
Short name T688
Test name
Test status
Simulation time 243118483 ps
CPU time 2.93 seconds
Started Jul 09 04:38:25 PM PDT 24
Finished Jul 09 04:38:28 PM PDT 24
Peak memory 196484 kb
Host smart-82ec51fc-1585-46c1-9c03-265988a3fa7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323725936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2323725936
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.636070111
Short name T382
Test name
Test status
Simulation time 48626015 ps
CPU time 0.95 seconds
Started Jul 09 04:38:26 PM PDT 24
Finished Jul 09 04:38:28 PM PDT 24
Peak memory 196348 kb
Host smart-489495b7-bc1b-4a8e-a070-099aa8dd6ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636070111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.636070111
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1815494685
Short name T412
Test name
Test status
Simulation time 27968634 ps
CPU time 1.04 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:25 PM PDT 24
Peak memory 196588 kb
Host smart-0d3e6cbf-1987-4af6-9fdd-4377bebea89f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815494685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1815494685
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2779414512
Short name T641
Test name
Test status
Simulation time 232522592 ps
CPU time 2.72 seconds
Started Jul 09 04:38:27 PM PDT 24
Finished Jul 09 04:38:30 PM PDT 24
Peak memory 198492 kb
Host smart-27136c7a-e1be-4069-b082-fffcd2ab1f97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779414512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2779414512
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3086762194
Short name T459
Test name
Test status
Simulation time 144678964 ps
CPU time 1.22 seconds
Started Jul 09 04:38:27 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 197460 kb
Host smart-cf53f56d-bb69-49f7-93d3-e80d8d699c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086762194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3086762194
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3894137762
Short name T499
Test name
Test status
Simulation time 175972325 ps
CPU time 0.93 seconds
Started Jul 09 04:38:23 PM PDT 24
Finished Jul 09 04:38:25 PM PDT 24
Peak memory 196176 kb
Host smart-22378462-c08f-46e0-ae99-8464dc336612
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894137762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3894137762
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3748246762
Short name T358
Test name
Test status
Simulation time 15329771 ps
CPU time 0.6 seconds
Started Jul 09 04:38:34 PM PDT 24
Finished Jul 09 04:38:36 PM PDT 24
Peak memory 194688 kb
Host smart-ccf27a07-a632-4f9e-81ee-f34027d74b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748246762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3748246762
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1545401071
Short name T547
Test name
Test status
Simulation time 30106042 ps
CPU time 0.61 seconds
Started Jul 09 04:38:28 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 194396 kb
Host smart-c4bebff1-6d0e-4c9e-893e-3bff71ca34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545401071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1545401071
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.710251580
Short name T140
Test name
Test status
Simulation time 3590005970 ps
CPU time 6.05 seconds
Started Jul 09 04:38:29 PM PDT 24
Finished Jul 09 04:38:36 PM PDT 24
Peak memory 197104 kb
Host smart-27d51ccc-849d-493f-9e61-b3c187ce1b1f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710251580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.710251580
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3864766968
Short name T696
Test name
Test status
Simulation time 110246002 ps
CPU time 0.87 seconds
Started Jul 09 04:38:30 PM PDT 24
Finished Jul 09 04:38:32 PM PDT 24
Peak memory 196520 kb
Host smart-a70e9789-70d5-401c-aadd-82707fd40c03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864766968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3864766968
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.874842762
Short name T610
Test name
Test status
Simulation time 141741017 ps
CPU time 1.25 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 196744 kb
Host smart-e7811d10-f62e-4ff7-ad95-9a496ad949cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874842762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.874842762
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2324601829
Short name T381
Test name
Test status
Simulation time 469119498 ps
CPU time 3.17 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:35 PM PDT 24
Peak memory 198604 kb
Host smart-e824f6ff-2b62-4d27-abeb-c5079319d427
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324601829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2324601829
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2554263114
Short name T130
Test name
Test status
Simulation time 534557352 ps
CPU time 1.51 seconds
Started Jul 09 04:38:29 PM PDT 24
Finished Jul 09 04:38:32 PM PDT 24
Peak memory 196620 kb
Host smart-14b1829d-854a-461f-b88a-40d10ce686b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554263114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2554263114
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.751863922
Short name T572
Test name
Test status
Simulation time 77564210 ps
CPU time 1.07 seconds
Started Jul 09 04:38:28 PM PDT 24
Finished Jul 09 04:38:30 PM PDT 24
Peak memory 196772 kb
Host smart-5457ce07-17dc-4810-a5da-d413e05f7e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751863922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.751863922
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2730003700
Short name T60
Test name
Test status
Simulation time 132546628 ps
CPU time 1.24 seconds
Started Jul 09 04:38:27 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 197516 kb
Host smart-646c7de3-8ed3-44c6-a152-cc2ea77b93bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730003700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2730003700
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1460144481
Short name T528
Test name
Test status
Simulation time 38171658 ps
CPU time 1.64 seconds
Started Jul 09 04:38:28 PM PDT 24
Finished Jul 09 04:38:31 PM PDT 24
Peak memory 198488 kb
Host smart-aa798621-6c03-40ad-9464-4a754aedd1ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460144481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1460144481
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2434992559
Short name T675
Test name
Test status
Simulation time 34824318 ps
CPU time 0.76 seconds
Started Jul 09 04:38:28 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 195848 kb
Host smart-253ffb13-edfd-4663-818c-21af0070371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434992559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2434992559
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1145589960
Short name T527
Test name
Test status
Simulation time 157615758 ps
CPU time 0.83 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 195744 kb
Host smart-1e230f52-7f15-4414-b2d8-eb8e84856c46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145589960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1145589960
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1161441659
Short name T210
Test name
Test status
Simulation time 4240668999 ps
CPU time 118.78 seconds
Started Jul 09 04:38:32 PM PDT 24
Finished Jul 09 04:40:32 PM PDT 24
Peak memory 198660 kb
Host smart-830e7166-3958-4446-a253-b3bcea9f4b3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161441659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1161441659
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1951391455
Short name T293
Test name
Test status
Simulation time 335364449011 ps
CPU time 1193.67 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:58:26 PM PDT 24
Peak memory 198796 kb
Host smart-8a47e4cf-a6bd-4840-b9bf-99c72485d8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1951391455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1951391455
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2957869615
Short name T715
Test name
Test status
Simulation time 55422075 ps
CPU time 0.56 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 194748 kb
Host smart-99b4c0e6-b46e-4717-b9d5-421ef270f52a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957869615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2957869615
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.770370010
Short name T695
Test name
Test status
Simulation time 198801049 ps
CPU time 0.96 seconds
Started Jul 09 04:38:32 PM PDT 24
Finished Jul 09 04:38:34 PM PDT 24
Peak memory 197252 kb
Host smart-caa30487-ec34-4d7e-b523-dd4cce4941b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770370010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.770370010
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.369664594
Short name T336
Test name
Test status
Simulation time 969993015 ps
CPU time 26.06 seconds
Started Jul 09 04:38:33 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 197244 kb
Host smart-2f8b2387-aafd-4611-a3a0-f1f6842a3489
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369664594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.369664594
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1752867331
Short name T717
Test name
Test status
Simulation time 43222397 ps
CPU time 0.82 seconds
Started Jul 09 04:38:33 PM PDT 24
Finished Jul 09 04:38:35 PM PDT 24
Peak memory 196532 kb
Host smart-c8122174-9b69-4264-b65d-8311eb496814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752867331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1752867331
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4139572575
Short name T347
Test name
Test status
Simulation time 93570859 ps
CPU time 0.72 seconds
Started Jul 09 04:38:34 PM PDT 24
Finished Jul 09 04:38:35 PM PDT 24
Peak memory 196680 kb
Host smart-d923e484-af52-4f7e-bee6-e3fa2d7b312a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139572575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4139572575
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1318864493
Short name T285
Test name
Test status
Simulation time 84214693 ps
CPU time 3.28 seconds
Started Jul 09 04:38:32 PM PDT 24
Finished Jul 09 04:38:37 PM PDT 24
Peak memory 198660 kb
Host smart-334f1dc1-ecca-4728-9936-173ee7d1ddeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318864493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1318864493
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2972964050
Short name T283
Test name
Test status
Simulation time 44646468 ps
CPU time 1.42 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:34 PM PDT 24
Peak memory 196688 kb
Host smart-599475e8-0f2f-43df-89b8-f547e970c532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972964050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2972964050
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1425202414
Short name T601
Test name
Test status
Simulation time 285263965 ps
CPU time 1.29 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:34 PM PDT 24
Peak memory 197640 kb
Host smart-ac6fea6a-f003-421e-bcbd-4327eb2e357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425202414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1425202414
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3678912211
Short name T341
Test name
Test status
Simulation time 230682605 ps
CPU time 1 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 196576 kb
Host smart-ff529bc3-7603-4a2c-a80f-b352c9d5c905
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678912211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3678912211
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3208187318
Short name T487
Test name
Test status
Simulation time 203053075 ps
CPU time 4.25 seconds
Started Jul 09 04:38:33 PM PDT 24
Finished Jul 09 04:38:38 PM PDT 24
Peak memory 198512 kb
Host smart-dec6339c-3f28-4546-9ed7-d180781c3daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208187318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3208187318
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.252993237
Short name T224
Test name
Test status
Simulation time 145582996 ps
CPU time 1.09 seconds
Started Jul 09 04:38:32 PM PDT 24
Finished Jul 09 04:38:34 PM PDT 24
Peak memory 196076 kb
Host smart-78ea7fe6-db9c-422f-bf2c-8b290a3411e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252993237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.252993237
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4024263828
Short name T615
Test name
Test status
Simulation time 33677788 ps
CPU time 0.95 seconds
Started Jul 09 04:38:32 PM PDT 24
Finished Jul 09 04:38:34 PM PDT 24
Peak memory 196432 kb
Host smart-226b78bd-22dd-4f39-ba3e-6bfa6b93e077
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024263828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4024263828
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4069763487
Short name T21
Test name
Test status
Simulation time 40764921620 ps
CPU time 109.25 seconds
Started Jul 09 04:38:32 PM PDT 24
Finished Jul 09 04:40:23 PM PDT 24
Peak memory 198608 kb
Host smart-050e4aa0-5e32-4e76-b2a3-b53b06449074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069763487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4069763487
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.385964999
Short name T611
Test name
Test status
Simulation time 115250314824 ps
CPU time 1441.92 seconds
Started Jul 09 04:38:33 PM PDT 24
Finished Jul 09 05:02:36 PM PDT 24
Peak memory 198768 kb
Host smart-0ae8ebbd-9015-40ed-8d13-532da4397304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=385964999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.385964999
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.593745278
Short name T708
Test name
Test status
Simulation time 26457748 ps
CPU time 0.57 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:46 PM PDT 24
Peak memory 194720 kb
Host smart-5bb16b73-b6da-4a5c-b5c0-e5c5a3742769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593745278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.593745278
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2883744024
Short name T173
Test name
Test status
Simulation time 15328114 ps
CPU time 0.61 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:46 PM PDT 24
Peak memory 195128 kb
Host smart-54e117c6-8e0c-4725-93c0-d94f89591e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883744024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2883744024
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1292301416
Short name T142
Test name
Test status
Simulation time 312381496 ps
CPU time 10.42 seconds
Started Jul 09 04:37:43 PM PDT 24
Finished Jul 09 04:37:53 PM PDT 24
Peak memory 196056 kb
Host smart-b0491446-208e-4b9c-9e02-0dc2126ce204
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292301416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1292301416
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1724145836
Short name T566
Test name
Test status
Simulation time 67733653 ps
CPU time 0.77 seconds
Started Jul 09 04:37:48 PM PDT 24
Finished Jul 09 04:37:50 PM PDT 24
Peak memory 196368 kb
Host smart-516f1a87-c9ec-41d5-9d51-1239ef3788e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724145836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1724145836
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2238910690
Short name T96
Test name
Test status
Simulation time 268783982 ps
CPU time 1.05 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:45 PM PDT 24
Peak memory 196712 kb
Host smart-3f150fe9-b57f-4b0f-88d3-de02b0319b16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238910690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2238910690
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3077584593
Short name T461
Test name
Test status
Simulation time 91727200 ps
CPU time 3.29 seconds
Started Jul 09 04:37:41 PM PDT 24
Finished Jul 09 04:37:44 PM PDT 24
Peak memory 198648 kb
Host smart-a67d216e-2c82-4fbc-affe-88875cca603f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077584593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3077584593
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2688085296
Short name T684
Test name
Test status
Simulation time 68826107 ps
CPU time 1.52 seconds
Started Jul 09 04:37:46 PM PDT 24
Finished Jul 09 04:37:48 PM PDT 24
Peak memory 196564 kb
Host smart-d9cf9231-f50c-4314-871a-ad8ace29288f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688085296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2688085296
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1641880498
Short name T411
Test name
Test status
Simulation time 134625170 ps
CPU time 1.25 seconds
Started Jul 09 04:37:42 PM PDT 24
Finished Jul 09 04:37:44 PM PDT 24
Peak memory 197128 kb
Host smart-3b444408-bf5d-4215-8c1a-66f0704aada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641880498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1641880498
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3137973089
Short name T594
Test name
Test status
Simulation time 61152626 ps
CPU time 1.24 seconds
Started Jul 09 04:37:43 PM PDT 24
Finished Jul 09 04:37:45 PM PDT 24
Peak memory 196340 kb
Host smart-ad3a4a86-ba4c-4f62-9632-64edaf157c44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137973089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3137973089
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1643590361
Short name T563
Test name
Test status
Simulation time 884174878 ps
CPU time 4.82 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:49 PM PDT 24
Peak memory 198540 kb
Host smart-9b88ee29-128a-4900-9e7f-98fa04ff49ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643590361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1643590361
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.692836895
Short name T31
Test name
Test status
Simulation time 81176950 ps
CPU time 0.84 seconds
Started Jul 09 04:37:40 PM PDT 24
Finished Jul 09 04:37:42 PM PDT 24
Peak memory 214248 kb
Host smart-9f5e00f0-f97d-492d-a51f-c50ae000f1b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692836895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.692836895
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.415932029
Short name T497
Test name
Test status
Simulation time 74203470 ps
CPU time 1.22 seconds
Started Jul 09 04:37:45 PM PDT 24
Finished Jul 09 04:37:47 PM PDT 24
Peak memory 196384 kb
Host smart-71fcd18e-6ecb-4ce3-9264-1df502f5d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415932029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.415932029
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.625879505
Short name T523
Test name
Test status
Simulation time 146396309 ps
CPU time 1.1 seconds
Started Jul 09 04:37:48 PM PDT 24
Finished Jul 09 04:37:51 PM PDT 24
Peak memory 195972 kb
Host smart-368ab16c-80d8-432b-a67e-8e316f2a169e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625879505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.625879505
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.919741806
Short name T46
Test name
Test status
Simulation time 45240982232 ps
CPU time 148.69 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:40:13 PM PDT 24
Peak memory 198744 kb
Host smart-c1642b99-fd2b-42ac-974e-51629a6b17d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919741806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.919741806
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.972791207
Short name T158
Test name
Test status
Simulation time 39330953 ps
CPU time 0.61 seconds
Started Jul 09 04:38:38 PM PDT 24
Finished Jul 09 04:38:39 PM PDT 24
Peak memory 195216 kb
Host smart-88e03d60-1892-4fc1-a73a-08b2522087c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972791207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.972791207
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3620010354
Short name T557
Test name
Test status
Simulation time 35500688 ps
CPU time 0.63 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 194532 kb
Host smart-0cf2ea36-f5c1-4e92-8a65-bf453a65e333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620010354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3620010354
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2137754610
Short name T503
Test name
Test status
Simulation time 2746331878 ps
CPU time 22.23 seconds
Started Jul 09 04:38:37 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 197612 kb
Host smart-590a1074-d0c0-449b-b58d-b5985fd5ed1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137754610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2137754610
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2113956672
Short name T623
Test name
Test status
Simulation time 75992950 ps
CPU time 0.92 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 04:38:38 PM PDT 24
Peak memory 197752 kb
Host smart-decd92a6-8c84-4846-953f-3fa964fcaa31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113956672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2113956672
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2891595007
Short name T344
Test name
Test status
Simulation time 77395016 ps
CPU time 1.07 seconds
Started Jul 09 04:38:38 PM PDT 24
Finished Jul 09 04:38:40 PM PDT 24
Peak memory 197360 kb
Host smart-b50d7ff8-645b-4f74-8304-9d511e790273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891595007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2891595007
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1086322682
Short name T703
Test name
Test status
Simulation time 265400258 ps
CPU time 2.81 seconds
Started Jul 09 04:38:38 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 198480 kb
Host smart-7d81eafe-f987-41ae-b5e7-eab4f99d3868
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086322682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1086322682
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.485924536
Short name T540
Test name
Test status
Simulation time 78366274 ps
CPU time 1.59 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 04:38:38 PM PDT 24
Peak memory 196712 kb
Host smart-8cbc2a12-4bc0-4587-b96e-bc66a4ff9580
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485924536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
485924536
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.524866127
Short name T440
Test name
Test status
Simulation time 108354694 ps
CPU time 1.06 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 196704 kb
Host smart-13b5e48f-9fba-44f4-8c6f-354963625d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524866127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.524866127
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2170234808
Short name T448
Test name
Test status
Simulation time 15435802 ps
CPU time 0.65 seconds
Started Jul 09 04:38:33 PM PDT 24
Finished Jul 09 04:38:34 PM PDT 24
Peak memory 194796 kb
Host smart-cf09acb5-dae4-4a12-b7fc-c51f8a4757e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170234808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2170234808
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3545119531
Short name T165
Test name
Test status
Simulation time 272226026 ps
CPU time 6.15 seconds
Started Jul 09 04:38:37 PM PDT 24
Finished Jul 09 04:38:45 PM PDT 24
Peak memory 198444 kb
Host smart-1c6f8337-1023-47f9-a9ef-681f34700495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545119531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3545119531
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.728625749
Short name T467
Test name
Test status
Simulation time 371757818 ps
CPU time 1.03 seconds
Started Jul 09 04:38:31 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 196100 kb
Host smart-62c33fb7-445f-4ceb-b616-36bbb9a6d487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728625749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.728625749
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4217890142
Short name T186
Test name
Test status
Simulation time 52566732 ps
CPU time 1.21 seconds
Started Jul 09 04:38:33 PM PDT 24
Finished Jul 09 04:38:35 PM PDT 24
Peak memory 196400 kb
Host smart-a7dd76d9-ff21-419a-93a8-ecb380c92148
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217890142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4217890142
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2630069453
Short name T296
Test name
Test status
Simulation time 31923803195 ps
CPU time 756.48 seconds
Started Jul 09 04:38:37 PM PDT 24
Finished Jul 09 04:51:14 PM PDT 24
Peak memory 198812 kb
Host smart-2e27dfa0-3696-4969-ae8b-cadbd8f06406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2630069453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2630069453
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1506499404
Short name T657
Test name
Test status
Simulation time 33206221 ps
CPU time 0.55 seconds
Started Jul 09 04:38:38 PM PDT 24
Finished Jul 09 04:38:40 PM PDT 24
Peak memory 194668 kb
Host smart-43e52271-fce0-4e66-aa32-0779b872fefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506499404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1506499404
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3998401208
Short name T427
Test name
Test status
Simulation time 100133612 ps
CPU time 0.89 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 04:38:38 PM PDT 24
Peak memory 197348 kb
Host smart-68895a88-cc96-4c77-a98b-86555b0015ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998401208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3998401208
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3215416212
Short name T311
Test name
Test status
Simulation time 357732056 ps
CPU time 8.34 seconds
Started Jul 09 04:38:37 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 197508 kb
Host smart-7e532fc9-a928-4e6f-bb12-6ed605187ed9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215416212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3215416212
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1344459442
Short name T539
Test name
Test status
Simulation time 404746097 ps
CPU time 0.69 seconds
Started Jul 09 04:38:38 PM PDT 24
Finished Jul 09 04:38:40 PM PDT 24
Peak memory 195840 kb
Host smart-a7d6ab84-1ebd-4315-b687-3c815dfc3ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344459442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1344459442
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4101690676
Short name T639
Test name
Test status
Simulation time 134077698 ps
CPU time 0.7 seconds
Started Jul 09 04:38:35 PM PDT 24
Finished Jul 09 04:38:37 PM PDT 24
Peak memory 196004 kb
Host smart-d88364fb-5d39-4bbc-be1f-e1853b7aa2da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101690676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4101690676
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1694959730
Short name T469
Test name
Test status
Simulation time 313534291 ps
CPU time 3.07 seconds
Started Jul 09 04:38:35 PM PDT 24
Finished Jul 09 04:38:39 PM PDT 24
Peak memory 198712 kb
Host smart-9a2e2224-44b6-4455-baf1-e6f16cde450d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694959730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1694959730
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.606679927
Short name T484
Test name
Test status
Simulation time 508977911 ps
CPU time 3.58 seconds
Started Jul 09 04:38:37 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 198516 kb
Host smart-0c0cad70-a225-4b37-b0f4-e39de88e7134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606679927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
606679927
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1305284828
Short name T524
Test name
Test status
Simulation time 270988255 ps
CPU time 1.38 seconds
Started Jul 09 04:38:39 PM PDT 24
Finished Jul 09 04:38:41 PM PDT 24
Peak memory 197384 kb
Host smart-bad7fb8b-46bc-4a64-a042-1b6805a6a982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305284828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1305284828
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2002489627
Short name T227
Test name
Test status
Simulation time 34695167 ps
CPU time 1.07 seconds
Started Jul 09 04:38:39 PM PDT 24
Finished Jul 09 04:38:41 PM PDT 24
Peak memory 197224 kb
Host smart-96bcb4e5-0659-44be-8b48-0bd347c31f4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002489627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2002489627
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3247189546
Short name T225
Test name
Test status
Simulation time 65695495 ps
CPU time 2.83 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 04:38:40 PM PDT 24
Peak memory 198620 kb
Host smart-25bcfbba-3b2d-49e8-a25a-62f7e5ff4dca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247189546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3247189546
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1031589900
Short name T45
Test name
Test status
Simulation time 31413274 ps
CPU time 0.8 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 04:38:38 PM PDT 24
Peak memory 195844 kb
Host smart-8c53c5e3-bc38-4b71-aa04-0b6bfb3a091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031589900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1031589900
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.634250291
Short name T249
Test name
Test status
Simulation time 40513649 ps
CPU time 0.95 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 196296 kb
Host smart-9bc6e56a-5db4-4832-865b-e48abda41537
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634250291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.634250291
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3007697551
Short name T189
Test name
Test status
Simulation time 63297133635 ps
CPU time 222.58 seconds
Started Jul 09 04:38:38 PM PDT 24
Finished Jul 09 04:42:22 PM PDT 24
Peak memory 198696 kb
Host smart-7d969fbb-cb9b-479c-9f4a-2f6a5fd87a9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007697551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3007697551
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3922677263
Short name T54
Test name
Test status
Simulation time 1518126739813 ps
CPU time 1908.63 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 05:10:26 PM PDT 24
Peak memory 206988 kb
Host smart-4720c361-66dc-4f0d-8b64-c61981707818
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3922677263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3922677263
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4145155414
Short name T176
Test name
Test status
Simulation time 25562091 ps
CPU time 0.57 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:38:46 PM PDT 24
Peak memory 194644 kb
Host smart-05891433-4111-48e4-89b4-8ea466b2e46e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145155414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4145155414
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.157967128
Short name T330
Test name
Test status
Simulation time 68100838 ps
CPU time 0.77 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:38:48 PM PDT 24
Peak memory 195896 kb
Host smart-0210bb0a-02d0-40d6-856a-9eb6ef538a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157967128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.157967128
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1027627972
Short name T647
Test name
Test status
Simulation time 2501139709 ps
CPU time 12.65 seconds
Started Jul 09 04:38:44 PM PDT 24
Finished Jul 09 04:38:57 PM PDT 24
Peak memory 197452 kb
Host smart-0ab7a0ff-76b7-40ea-bffa-bd95c90fd899
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027627972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1027627972
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3814897340
Short name T435
Test name
Test status
Simulation time 38535838 ps
CPU time 0.72 seconds
Started Jul 09 04:38:43 PM PDT 24
Finished Jul 09 04:38:44 PM PDT 24
Peak memory 195180 kb
Host smart-1896d7a6-0bf2-4075-b23c-bdf476c9b96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814897340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3814897340
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1262996274
Short name T192
Test name
Test status
Simulation time 79060340 ps
CPU time 0.64 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 194784 kb
Host smart-8fbaec06-3871-4bbc-ad64-2b2330214aa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262996274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1262996274
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.178582103
Short name T441
Test name
Test status
Simulation time 54149080 ps
CPU time 2.08 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 198516 kb
Host smart-6993491a-e791-4971-a7b8-c98e2e67649f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178582103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.178582103
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2310378009
Short name T450
Test name
Test status
Simulation time 321757137 ps
CPU time 1.85 seconds
Started Jul 09 04:38:41 PM PDT 24
Finished Jul 09 04:38:44 PM PDT 24
Peak memory 196496 kb
Host smart-ac3ce836-1413-4ad4-ad4a-86b392fd697b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310378009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2310378009
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4009099284
Short name T444
Test name
Test status
Simulation time 39420241 ps
CPU time 0.97 seconds
Started Jul 09 04:38:37 PM PDT 24
Finished Jul 09 04:38:39 PM PDT 24
Peak memory 196792 kb
Host smart-f24c96b3-d4dc-4a3c-bf7a-170e930d2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009099284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4009099284
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.338968180
Short name T574
Test name
Test status
Simulation time 224117790 ps
CPU time 1.15 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 197048 kb
Host smart-9f6cc3f2-3274-493d-9a18-ea828973a48b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338968180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.338968180
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1941722742
Short name T494
Test name
Test status
Simulation time 71162231 ps
CPU time 3.18 seconds
Started Jul 09 04:38:42 PM PDT 24
Finished Jul 09 04:38:46 PM PDT 24
Peak memory 198492 kb
Host smart-e5965d98-3fc4-41e2-ac8b-d0538d839bf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941722742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1941722742
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2895527556
Short name T549
Test name
Test status
Simulation time 232556009 ps
CPU time 1.21 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:43 PM PDT 24
Peak memory 197264 kb
Host smart-f8046575-1c89-43ee-bbc2-d1a212c50c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895527556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2895527556
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.195380299
Short name T16
Test name
Test status
Simulation time 88641854 ps
CPU time 1.05 seconds
Started Jul 09 04:38:36 PM PDT 24
Finished Jul 09 04:38:38 PM PDT 24
Peak memory 196316 kb
Host smart-43f557d7-1fad-4a7e-80c7-64921ac973df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195380299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.195380299
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.21086180
Short name T591
Test name
Test status
Simulation time 3141601369 ps
CPU time 44.6 seconds
Started Jul 09 04:38:41 PM PDT 24
Finished Jul 09 04:39:27 PM PDT 24
Peak memory 198668 kb
Host smart-d02ca3f3-bacd-4b58-8de5-60e230dc6935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21086180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gp
io_stress_all.21086180
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2997025333
Short name T564
Test name
Test status
Simulation time 34080963 ps
CPU time 0.55 seconds
Started Jul 09 04:38:41 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 194508 kb
Host smart-e18e10fd-396b-48b1-b770-9281ca91f037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997025333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2997025333
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.4025754154
Short name T235
Test name
Test status
Simulation time 101612639 ps
CPU time 0.68 seconds
Started Jul 09 04:38:42 PM PDT 24
Finished Jul 09 04:38:43 PM PDT 24
Peak memory 195816 kb
Host smart-3b68b547-7ff3-4948-b0c0-0946b957240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025754154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.4025754154
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.170438956
Short name T522
Test name
Test status
Simulation time 461760711 ps
CPU time 12.14 seconds
Started Jul 09 04:38:47 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 197036 kb
Host smart-a6a61cfd-3694-4ac6-a559-9f69206f7606
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170438956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.170438956
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.4207524350
Short name T551
Test name
Test status
Simulation time 81844714 ps
CPU time 0.92 seconds
Started Jul 09 04:38:44 PM PDT 24
Finished Jul 09 04:38:46 PM PDT 24
Peak memory 198320 kb
Host smart-1c95c3eb-88cd-487e-bd08-0ae87fe1208f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207524350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.4207524350
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1951083029
Short name T380
Test name
Test status
Simulation time 143016841 ps
CPU time 0.87 seconds
Started Jul 09 04:38:41 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 196992 kb
Host smart-6f4ea30f-8125-437d-b862-e3d246190e35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951083029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1951083029
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3989644234
Short name T465
Test name
Test status
Simulation time 87892603 ps
CPU time 3.45 seconds
Started Jul 09 04:38:41 PM PDT 24
Finished Jul 09 04:38:46 PM PDT 24
Peak memory 198580 kb
Host smart-83a0b973-5a32-4cf2-987d-c4b7de49b8fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989644234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3989644234
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1742936887
Short name T372
Test name
Test status
Simulation time 89082233 ps
CPU time 0.89 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:41 PM PDT 24
Peak memory 196080 kb
Host smart-9724e4d9-75f5-4b40-92cc-6e2e6454f299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742936887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1742936887
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2810852450
Short name T343
Test name
Test status
Simulation time 30153122 ps
CPU time 1.06 seconds
Started Jul 09 04:38:42 PM PDT 24
Finished Jul 09 04:38:44 PM PDT 24
Peak memory 197076 kb
Host smart-009c23ae-5f15-45cc-82ee-22adcc1e488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810852450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2810852450
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.496224216
Short name T332
Test name
Test status
Simulation time 36817176 ps
CPU time 0.85 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:41 PM PDT 24
Peak memory 196616 kb
Host smart-5ed9c9db-37dc-470a-940e-9da9cee05011
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496224216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.496224216
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3159488288
Short name T666
Test name
Test status
Simulation time 669394023 ps
CPU time 3.85 seconds
Started Jul 09 04:38:42 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 198576 kb
Host smart-587a01bc-50c2-40e0-b1c7-8ce655c0e458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159488288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3159488288
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2132299193
Short name T147
Test name
Test status
Simulation time 85501333 ps
CPU time 1 seconds
Started Jul 09 04:38:40 PM PDT 24
Finished Jul 09 04:38:42 PM PDT 24
Peak memory 197008 kb
Host smart-97cbebd1-d90c-41c7-92d6-cd136ae6edb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132299193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2132299193
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.607713756
Short name T482
Test name
Test status
Simulation time 565516818 ps
CPU time 1.24 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 197336 kb
Host smart-7df3cafd-c815-4cd6-90c1-dbbe7699e2cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607713756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.607713756
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3199766218
Short name T409
Test name
Test status
Simulation time 6766242557 ps
CPU time 93.48 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:40:19 PM PDT 24
Peak memory 198624 kb
Host smart-93a4ea10-76f6-4cbf-b230-7843a196cdbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199766218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3199766218
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2788700314
Short name T56
Test name
Test status
Simulation time 478529795075 ps
CPU time 2381.56 seconds
Started Jul 09 04:38:42 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206944 kb
Host smart-04f5df08-521a-47d2-9b85-f8312ba50c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2788700314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2788700314
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.162187101
Short name T146
Test name
Test status
Simulation time 14057449 ps
CPU time 0.57 seconds
Started Jul 09 04:38:44 PM PDT 24
Finished Jul 09 04:38:45 PM PDT 24
Peak memory 194760 kb
Host smart-002de9c2-2254-499d-8e14-dde29daf619f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162187101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.162187101
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.708127589
Short name T663
Test name
Test status
Simulation time 102345274 ps
CPU time 0.84 seconds
Started Jul 09 04:38:44 PM PDT 24
Finished Jul 09 04:38:45 PM PDT 24
Peak memory 197796 kb
Host smart-01e458bf-6458-41d7-ad15-a2cb09fc98f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708127589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.708127589
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3282885724
Short name T201
Test name
Test status
Simulation time 2929988286 ps
CPU time 9.24 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 197416 kb
Host smart-7b13b8c2-6226-40b2-aeb2-06cd4c7714ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282885724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3282885724
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.877406057
Short name T553
Test name
Test status
Simulation time 156577113 ps
CPU time 0.7 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 194860 kb
Host smart-5f2c050c-94d8-466d-98b1-85d6d38f7168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877406057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.877406057
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.498543216
Short name T589
Test name
Test status
Simulation time 37628520 ps
CPU time 1.1 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 197472 kb
Host smart-d81c4e2f-be05-4808-b1a9-016aa9ee8635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498543216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.498543216
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2105938747
Short name T103
Test name
Test status
Simulation time 172753560 ps
CPU time 3.42 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:38:51 PM PDT 24
Peak memory 198628 kb
Host smart-ed61841c-7022-49a3-ac42-c2795a13018c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105938747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2105938747
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.42906219
Short name T388
Test name
Test status
Simulation time 53948234 ps
CPU time 1.67 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:38:48 PM PDT 24
Peak memory 196616 kb
Host smart-41601990-e55f-4f30-90c8-6365f5fad2b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.42906219
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1726381216
Short name T315
Test name
Test status
Simulation time 82106966 ps
CPU time 0.87 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:38:48 PM PDT 24
Peak memory 196092 kb
Host smart-c1e8e7c5-186c-4ee9-b599-a2c82ab4b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726381216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1726381216
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.875418354
Short name T375
Test name
Test status
Simulation time 29168449 ps
CPU time 0.82 seconds
Started Jul 09 04:38:48 PM PDT 24
Finished Jul 09 04:38:50 PM PDT 24
Peak memory 196036 kb
Host smart-3c55def9-da69-4911-9147-6bf6f749f0b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875418354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.875418354
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.799808245
Short name T667
Test name
Test status
Simulation time 60316094 ps
CPU time 1.5 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 198356 kb
Host smart-26888b84-2569-4edb-acda-a9fe11742f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799808245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.799808245
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1648345945
Short name T177
Test name
Test status
Simulation time 710174710 ps
CPU time 1.54 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:38:49 PM PDT 24
Peak memory 196156 kb
Host smart-803d4d8c-bab3-459c-b132-f8aa08b296db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648345945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1648345945
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.963729396
Short name T560
Test name
Test status
Simulation time 40428055 ps
CPU time 0.89 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:38:48 PM PDT 24
Peak memory 196028 kb
Host smart-d29206e4-8cd4-4812-a76a-4e6553b01543
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963729396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.963729396
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4200756984
Short name T583
Test name
Test status
Simulation time 1577968343 ps
CPU time 39.94 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:39:31 PM PDT 24
Peak memory 198472 kb
Host smart-972f0624-3f28-4381-af41-70a8d776151a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200756984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4200756984
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4242867199
Short name T424
Test name
Test status
Simulation time 12972430 ps
CPU time 0.56 seconds
Started Jul 09 04:38:47 PM PDT 24
Finished Jul 09 04:38:49 PM PDT 24
Peak memory 195260 kb
Host smart-cedd5fbe-ccfa-461d-a869-c494d84bff4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242867199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4242867199
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3133767153
Short name T139
Test name
Test status
Simulation time 50274248 ps
CPU time 0.85 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 196536 kb
Host smart-da45bdba-6375-4d3c-afc3-a7dfd2e837c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133767153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3133767153
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3213605854
Short name T320
Test name
Test status
Simulation time 1049037945 ps
CPU time 27.19 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 196808 kb
Host smart-76c127ea-8402-469e-9717-5809cf91c1d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213605854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3213605854
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.730945178
Short name T671
Test name
Test status
Simulation time 314138656 ps
CPU time 0.77 seconds
Started Jul 09 04:38:47 PM PDT 24
Finished Jul 09 04:38:49 PM PDT 24
Peak memory 197040 kb
Host smart-1a1f4779-7d86-4e3f-b39a-3cef1bc4258e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730945178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.730945178
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1366842188
Short name T593
Test name
Test status
Simulation time 23359600 ps
CPU time 0.77 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 196112 kb
Host smart-0ccf566d-c836-4d18-8987-caf1d41ecef7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366842188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1366842188
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4134075320
Short name T498
Test name
Test status
Simulation time 126023289 ps
CPU time 2.58 seconds
Started Jul 09 04:38:51 PM PDT 24
Finished Jul 09 04:38:55 PM PDT 24
Peak memory 197108 kb
Host smart-3a70148e-24a7-4335-8c33-413c6d2f4ae1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134075320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4134075320
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1492585237
Short name T287
Test name
Test status
Simulation time 119242363 ps
CPU time 3.51 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:38:51 PM PDT 24
Peak memory 198592 kb
Host smart-e0b96b56-fcf6-4aad-8e4e-7f5b436f4311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492585237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1492585237
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1002333145
Short name T458
Test name
Test status
Simulation time 211966899 ps
CPU time 1.19 seconds
Started Jul 09 04:38:44 PM PDT 24
Finished Jul 09 04:38:46 PM PDT 24
Peak memory 197508 kb
Host smart-d72e4c25-8a5e-43d0-bbac-127fb10efc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002333145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1002333145
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.993593542
Short name T246
Test name
Test status
Simulation time 48149858 ps
CPU time 1.04 seconds
Started Jul 09 04:38:44 PM PDT 24
Finished Jul 09 04:38:46 PM PDT 24
Peak memory 196596 kb
Host smart-bbb6042e-362d-4515-a78c-e2d8ec129653
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993593542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.993593542
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1042019172
Short name T255
Test name
Test status
Simulation time 393037607 ps
CPU time 3.5 seconds
Started Jul 09 04:38:48 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 198588 kb
Host smart-4e95805a-7826-40df-8b25-2c07557a4b3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042019172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1042019172
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3982226845
Short name T119
Test name
Test status
Simulation time 121629585 ps
CPU time 1.2 seconds
Started Jul 09 04:38:51 PM PDT 24
Finished Jul 09 04:38:54 PM PDT 24
Peak memory 197360 kb
Host smart-b93bc453-ee6d-4298-a0e3-6d4446e64451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982226845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3982226845
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3987654230
Short name T586
Test name
Test status
Simulation time 268091223 ps
CPU time 1.29 seconds
Started Jul 09 04:38:45 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 197252 kb
Host smart-4729054a-1b98-4540-989c-c166b0ff21f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987654230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3987654230
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.649339990
Short name T672
Test name
Test status
Simulation time 27736878387 ps
CPU time 154.75 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:41:26 PM PDT 24
Peak memory 198732 kb
Host smart-dc194c99-5829-4a1d-96c3-654ee2c350ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649339990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.649339990
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2955307322
Short name T248
Test name
Test status
Simulation time 34961569 ps
CPU time 0.64 seconds
Started Jul 09 04:38:51 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 194624 kb
Host smart-327bdfcc-e8bb-4519-8d4c-189fa3d16860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955307322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2955307322
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.278491772
Short name T267
Test name
Test status
Simulation time 37656648 ps
CPU time 0.91 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 196488 kb
Host smart-3f730775-38e9-44b5-bcfd-07808702c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278491772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.278491772
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1947866375
Short name T368
Test name
Test status
Simulation time 513250159 ps
CPU time 6.93 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:39:01 PM PDT 24
Peak memory 197560 kb
Host smart-4d67959c-2162-4e37-bc03-99e5b600bcf8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947866375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1947866375
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3172467445
Short name T492
Test name
Test status
Simulation time 38885469 ps
CPU time 0.79 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:38:56 PM PDT 24
Peak memory 196156 kb
Host smart-0ab257b4-347f-4c1e-927f-3a14b3dfe5df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172467445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3172467445
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2835683748
Short name T526
Test name
Test status
Simulation time 253175804 ps
CPU time 1.19 seconds
Started Jul 09 04:38:46 PM PDT 24
Finished Jul 09 04:38:48 PM PDT 24
Peak memory 196716 kb
Host smart-2b92da53-9e21-4d6f-8d0e-a186e79f5020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835683748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2835683748
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3452673489
Short name T167
Test name
Test status
Simulation time 89615099 ps
CPU time 2.95 seconds
Started Jul 09 04:38:52 PM PDT 24
Finished Jul 09 04:38:56 PM PDT 24
Peak memory 198564 kb
Host smart-d6f039d1-6c69-4323-88a4-c443bf7ae8a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452673489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3452673489
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.195224617
Short name T488
Test name
Test status
Simulation time 2616558775 ps
CPU time 2.52 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 197888 kb
Host smart-1bd68053-9131-4e59-8a86-695500455e8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195224617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
195224617
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2801889810
Short name T433
Test name
Test status
Simulation time 98957437 ps
CPU time 1.11 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 196332 kb
Host smart-1c6bf0d3-0097-4572-9fef-97201f38c4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801889810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2801889810
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3560214403
Short name T48
Test name
Test status
Simulation time 24317052 ps
CPU time 0.92 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 196488 kb
Host smart-db22b187-5215-44dd-bed5-65dc55bb8a3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560214403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3560214403
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.427276299
Short name T706
Test name
Test status
Simulation time 2181065456 ps
CPU time 3.95 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 198596 kb
Host smart-72e1b293-df7f-4a92-946f-365c20d4dc2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427276299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.427276299
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3873986557
Short name T562
Test name
Test status
Simulation time 94411297 ps
CPU time 0.91 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 196716 kb
Host smart-51fe0be3-1003-4333-84e5-af7c023b7ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873986557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3873986557
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3553500270
Short name T400
Test name
Test status
Simulation time 56288947 ps
CPU time 1.01 seconds
Started Jul 09 04:38:47 PM PDT 24
Finished Jul 09 04:38:50 PM PDT 24
Peak memory 196660 kb
Host smart-ea77a880-696f-4e04-91f4-7d60581f8e0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553500270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3553500270
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1448283971
Short name T273
Test name
Test status
Simulation time 4397528792 ps
CPU time 30.02 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:39:22 PM PDT 24
Peak memory 198684 kb
Host smart-b5a126d2-9c32-488a-980b-543e46fbe74b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448283971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1448283971
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3416715276
Short name T325
Test name
Test status
Simulation time 82384092749 ps
CPU time 1236.34 seconds
Started Jul 09 04:38:48 PM PDT 24
Finished Jul 09 04:59:25 PM PDT 24
Peak memory 199220 kb
Host smart-9c105971-0b7d-4692-8cc3-9fc6400a65b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3416715276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3416715276
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3576750323
Short name T451
Test name
Test status
Simulation time 40747136 ps
CPU time 0.55 seconds
Started Jul 09 04:38:48 PM PDT 24
Finished Jul 09 04:38:50 PM PDT 24
Peak memory 194520 kb
Host smart-e23148f5-0456-47b8-8a28-baea500f2184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576750323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3576750323
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.579092068
Short name T399
Test name
Test status
Simulation time 45560798 ps
CPU time 0.92 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 197136 kb
Host smart-f349a563-2670-4132-9834-56d80b063007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579092068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.579092068
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.527694392
Short name T678
Test name
Test status
Simulation time 88054046 ps
CPU time 3.83 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:38:56 PM PDT 24
Peak memory 196504 kb
Host smart-7a0d7b88-2b50-4fbe-9806-0df0d7f3bfd3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527694392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.527694392
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3181047200
Short name T153
Test name
Test status
Simulation time 278143526 ps
CPU time 0.96 seconds
Started Jul 09 04:38:55 PM PDT 24
Finished Jul 09 04:38:56 PM PDT 24
Peak memory 197404 kb
Host smart-e2a1305a-fe6c-4ed4-a695-4713b916001f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181047200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3181047200
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.754395867
Short name T690
Test name
Test status
Simulation time 299528038 ps
CPU time 1.18 seconds
Started Jul 09 04:38:48 PM PDT 24
Finished Jul 09 04:38:51 PM PDT 24
Peak memory 196412 kb
Host smart-589d3edb-da31-4bd6-8e73-d439dc957cab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754395867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.754395867
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1480586802
Short name T654
Test name
Test status
Simulation time 109424278 ps
CPU time 1.38 seconds
Started Jul 09 04:38:53 PM PDT 24
Finished Jul 09 04:38:55 PM PDT 24
Peak memory 197308 kb
Host smart-c693ec1a-2b24-496c-a021-5a1f4441ca41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480586802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1480586802
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1531621270
Short name T640
Test name
Test status
Simulation time 439680396 ps
CPU time 2.43 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:54 PM PDT 24
Peak memory 197504 kb
Host smart-78872672-74b2-4aef-bf26-b152b29966aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531621270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1531621270
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3064947487
Short name T349
Test name
Test status
Simulation time 34809065 ps
CPU time 0.66 seconds
Started Jul 09 04:38:59 PM PDT 24
Finished Jul 09 04:39:01 PM PDT 24
Peak memory 194904 kb
Host smart-fe94343e-bcce-4a70-b782-e17a1d04c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064947487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3064947487
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1556747257
Short name T328
Test name
Test status
Simulation time 54113409 ps
CPU time 1.25 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 197648 kb
Host smart-3e01f1f5-6703-4f28-8ed8-38cf1f6b3708
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556747257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1556747257
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.820246326
Short name T431
Test name
Test status
Simulation time 79927744 ps
CPU time 3.02 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:54 PM PDT 24
Peak memory 198408 kb
Host smart-446f276b-f015-4da1-b6ea-28c13cdc5e79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820246326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.820246326
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.855366583
Short name T604
Test name
Test status
Simulation time 381400156 ps
CPU time 1.24 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:51 PM PDT 24
Peak memory 196104 kb
Host smart-dde9cd3e-82cf-4ea4-99c5-75089e720355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855366583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.855366583
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1103944249
Short name T468
Test name
Test status
Simulation time 28446824 ps
CPU time 0.79 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 195736 kb
Host smart-7949013b-d064-4180-9506-58e043eda67f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103944249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1103944249
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.301839574
Short name T674
Test name
Test status
Simulation time 5858748599 ps
CPU time 78.6 seconds
Started Jul 09 04:38:50 PM PDT 24
Finished Jul 09 04:40:11 PM PDT 24
Peak memory 198668 kb
Host smart-34695166-a138-4258-9c97-a67795f4912d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301839574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.301839574
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1728071218
Short name T87
Test name
Test status
Simulation time 253398107640 ps
CPU time 3001.57 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 05:28:52 PM PDT 24
Peak memory 198832 kb
Host smart-ac7ee078-92a9-433b-b048-d2d4ea6b18d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1728071218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1728071218
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3012351803
Short name T333
Test name
Test status
Simulation time 11768877 ps
CPU time 0.59 seconds
Started Jul 09 04:38:57 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 194512 kb
Host smart-267c7234-5541-48ed-8f27-eae5015a4ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012351803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3012351803
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2821426535
Short name T156
Test name
Test status
Simulation time 90503967 ps
CPU time 0.65 seconds
Started Jul 09 04:38:51 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 194536 kb
Host smart-2f66a823-1a22-4158-bdf9-4ea518a31a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821426535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2821426535
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1190193612
Short name T511
Test name
Test status
Simulation time 1131677652 ps
CPU time 13.92 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:39:08 PM PDT 24
Peak memory 197540 kb
Host smart-46fd7ff6-82ce-4619-a787-db67fb22279c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190193612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1190193612
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4104738678
Short name T496
Test name
Test status
Simulation time 143832659 ps
CPU time 0.77 seconds
Started Jul 09 04:38:53 PM PDT 24
Finished Jul 09 04:38:55 PM PDT 24
Peak memory 196556 kb
Host smart-f6627de8-d6cd-4a08-a37f-37e457dde2c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104738678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4104738678
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1339965396
Short name T537
Test name
Test status
Simulation time 158343150 ps
CPU time 0.93 seconds
Started Jul 09 04:38:48 PM PDT 24
Finished Jul 09 04:38:50 PM PDT 24
Peak memory 196644 kb
Host smart-7c03f985-9d0d-4a09-9e50-ab7d668058d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339965396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1339965396
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.377132866
Short name T629
Test name
Test status
Simulation time 59572965 ps
CPU time 2.28 seconds
Started Jul 09 04:38:53 PM PDT 24
Finished Jul 09 04:38:56 PM PDT 24
Peak memory 197004 kb
Host smart-ddc8495e-0dbe-40b5-b4c8-18a56ffcdb8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377132866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.377132866
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3442245623
Short name T61
Test name
Test status
Simulation time 166915298 ps
CPU time 1.42 seconds
Started Jul 09 04:38:57 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 196224 kb
Host smart-058f8fd4-c793-47c9-9bc9-e13b867c734c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442245623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3442245623
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.66485771
Short name T432
Test name
Test status
Simulation time 39046579 ps
CPU time 0.8 seconds
Started Jul 09 04:38:48 PM PDT 24
Finished Jul 09 04:38:51 PM PDT 24
Peak memory 197092 kb
Host smart-27ff859b-1299-46d4-9aa8-8e36d3fa291b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66485771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.66485771
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.33602457
Short name T365
Test name
Test status
Simulation time 26055293 ps
CPU time 0.67 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:51 PM PDT 24
Peak memory 194800 kb
Host smart-34e90e8b-51ba-419b-ae19-0bbd004756bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33602457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup_
pulldown.33602457
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1808280430
Short name T7
Test name
Test status
Simulation time 409609167 ps
CPU time 5.24 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 198516 kb
Host smart-bedb9036-69b6-424e-8354-5cd9ecc239ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808280430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1808280430
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2353783169
Short name T233
Test name
Test status
Simulation time 61260826 ps
CPU time 1.17 seconds
Started Jul 09 04:38:57 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 195980 kb
Host smart-72984ad2-ce8a-47a8-a275-dc54605b9a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353783169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2353783169
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3066637243
Short name T627
Test name
Test status
Simulation time 154512925 ps
CPU time 1.17 seconds
Started Jul 09 04:38:49 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 196772 kb
Host smart-7e023b56-b42c-4416-9ccf-0a3c98ed687c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066637243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3066637243
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2827552020
Short name T700
Test name
Test status
Simulation time 6080664245 ps
CPU time 157.24 seconds
Started Jul 09 04:38:52 PM PDT 24
Finished Jul 09 04:41:31 PM PDT 24
Peak memory 198660 kb
Host smart-0663b351-f248-4491-9bd6-5cac6e4ba581
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827552020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2827552020
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3531490696
Short name T58
Test name
Test status
Simulation time 128360437693 ps
CPU time 555.94 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:48:11 PM PDT 24
Peak memory 198808 kb
Host smart-307168f0-1be5-4e30-8ec7-7463e9c02c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3531490696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3531490696
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3398575169
Short name T410
Test name
Test status
Simulation time 19676814 ps
CPU time 0.57 seconds
Started Jul 09 04:39:00 PM PDT 24
Finished Jul 09 04:39:02 PM PDT 24
Peak memory 194636 kb
Host smart-7093eea6-097f-422f-b224-f2f4ff73be53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398575169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3398575169
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2135537793
Short name T212
Test name
Test status
Simulation time 127583561 ps
CPU time 0.86 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 197664 kb
Host smart-c2d407ce-72d1-4721-9fac-5cde68e4106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135537793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2135537793
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.224334274
Short name T673
Test name
Test status
Simulation time 91998947 ps
CPU time 5.09 seconds
Started Jul 09 04:39:00 PM PDT 24
Finished Jul 09 04:39:06 PM PDT 24
Peak memory 196984 kb
Host smart-6a79ce58-14d3-4bcf-a516-7178451d2374
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224334274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.224334274
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3576132189
Short name T137
Test name
Test status
Simulation time 91384887 ps
CPU time 0.74 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 196420 kb
Host smart-71d66abc-1a52-41a8-8def-9341480e8b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576132189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3576132189
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3605846715
Short name T607
Test name
Test status
Simulation time 25542904 ps
CPU time 0.8 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:38:55 PM PDT 24
Peak memory 195680 kb
Host smart-b9bd2b8a-eb30-4b9b-a671-2a9bddbb25ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605846715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3605846715
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4107422554
Short name T616
Test name
Test status
Simulation time 137523858 ps
CPU time 1.54 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:39:01 PM PDT 24
Peak memory 198608 kb
Host smart-f2326208-caa0-499e-986c-2e270e82eb2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107422554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4107422554
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.205517740
Short name T648
Test name
Test status
Simulation time 29291965 ps
CPU time 1.04 seconds
Started Jul 09 04:38:53 PM PDT 24
Finished Jul 09 04:38:55 PM PDT 24
Peak memory 196088 kb
Host smart-e43e1e29-69ee-4336-b627-d35225f2fa8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205517740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
205517740
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.373840295
Short name T117
Test name
Test status
Simulation time 109406861 ps
CPU time 1.02 seconds
Started Jul 09 04:38:56 PM PDT 24
Finished Jul 09 04:38:58 PM PDT 24
Peak memory 196572 kb
Host smart-1ab0fabf-6499-4219-8728-8a76c4f45822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373840295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.373840295
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2795149286
Short name T196
Test name
Test status
Simulation time 28814264 ps
CPU time 1.14 seconds
Started Jul 09 04:38:54 PM PDT 24
Finished Jul 09 04:38:56 PM PDT 24
Peak memory 197252 kb
Host smart-775f9f23-2e84-47eb-8bef-4711d16c21fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795149286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2795149286
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1325321027
Short name T288
Test name
Test status
Simulation time 394253326 ps
CPU time 2.13 seconds
Started Jul 09 04:38:57 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 198472 kb
Host smart-15ff805d-6558-4ea6-aec7-76fa3d39d32d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325321027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1325321027
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1425159671
Short name T587
Test name
Test status
Simulation time 105144527 ps
CPU time 0.85 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 196464 kb
Host smart-011d50f4-8a28-4c36-8bce-1f2816895828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425159671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1425159671
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1083526560
Short name T504
Test name
Test status
Simulation time 38286584 ps
CPU time 0.98 seconds
Started Jul 09 04:38:57 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 196304 kb
Host smart-e6bf8389-b1b9-4f3c-8b1b-f1de385a7b29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083526560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1083526560
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3197772549
Short name T711
Test name
Test status
Simulation time 25047637520 ps
CPU time 63.88 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:40:03 PM PDT 24
Peak memory 198600 kb
Host smart-3d41d878-7ef3-4c99-88a8-e81f77642daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197772549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3197772549
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3512291671
Short name T536
Test name
Test status
Simulation time 13106727 ps
CPU time 0.56 seconds
Started Jul 09 04:37:52 PM PDT 24
Finished Jul 09 04:37:53 PM PDT 24
Peak memory 195136 kb
Host smart-d48877ec-cb1e-4716-a34f-3fcd46fa2ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512291671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3512291671
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2145872974
Short name T218
Test name
Test status
Simulation time 17901948 ps
CPU time 0.58 seconds
Started Jul 09 04:37:40 PM PDT 24
Finished Jul 09 04:37:41 PM PDT 24
Peak memory 194508 kb
Host smart-b80b7d5d-74eb-4279-8503-090392ff86aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145872974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2145872974
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2679347241
Short name T259
Test name
Test status
Simulation time 262659040 ps
CPU time 6.84 seconds
Started Jul 09 04:37:47 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 198496 kb
Host smart-82b9602c-c42d-48d8-af81-c7caa04aa76e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679347241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2679347241
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2074728298
Short name T214
Test name
Test status
Simulation time 70705861 ps
CPU time 0.68 seconds
Started Jul 09 04:37:45 PM PDT 24
Finished Jul 09 04:37:46 PM PDT 24
Peak memory 195300 kb
Host smart-920e5c45-9aa9-42a7-88c2-38668ea845ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074728298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2074728298
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1652441692
Short name T396
Test name
Test status
Simulation time 32782765 ps
CPU time 0.77 seconds
Started Jul 09 04:37:43 PM PDT 24
Finished Jul 09 04:37:44 PM PDT 24
Peak memory 196200 kb
Host smart-0be8a4a6-e733-44fd-a43b-99d8f17c2edb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652441692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1652441692
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3661314489
Short name T682
Test name
Test status
Simulation time 19418416 ps
CPU time 0.97 seconds
Started Jul 09 04:37:48 PM PDT 24
Finished Jul 09 04:37:50 PM PDT 24
Peak memory 196624 kb
Host smart-25a3d28c-40bc-45d8-bcac-b804609b363c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661314489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3661314489
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.412767522
Short name T416
Test name
Test status
Simulation time 286167917 ps
CPU time 3.09 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:48 PM PDT 24
Peak memory 197828 kb
Host smart-824ca7d7-b719-4f19-8618-992a48c88839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412767522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.412767522
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3342996291
Short name T369
Test name
Test status
Simulation time 25352260 ps
CPU time 0.67 seconds
Started Jul 09 04:37:45 PM PDT 24
Finished Jul 09 04:37:47 PM PDT 24
Peak memory 194816 kb
Host smart-d4ee5439-13b6-4172-ae04-d04c86863f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342996291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3342996291
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1255289554
Short name T545
Test name
Test status
Simulation time 57969584 ps
CPU time 1.22 seconds
Started Jul 09 04:37:43 PM PDT 24
Finished Jul 09 04:37:45 PM PDT 24
Peak memory 196380 kb
Host smart-a0e28124-b9d3-418b-9e13-32eefce7ffb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255289554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1255289554
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4107470717
Short name T543
Test name
Test status
Simulation time 282576887 ps
CPU time 3.29 seconds
Started Jul 09 04:37:46 PM PDT 24
Finished Jul 09 04:37:50 PM PDT 24
Peak memory 198424 kb
Host smart-9a72b87d-eca4-4731-ae8c-f9c97eba9cee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107470717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4107470717
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2959214031
Short name T41
Test name
Test status
Simulation time 130286313 ps
CPU time 0.81 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:37:46 PM PDT 24
Peak memory 214064 kb
Host smart-84d20fc8-1e57-44b7-9873-905abba35f98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959214031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2959214031
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2648830616
Short name T438
Test name
Test status
Simulation time 790626291 ps
CPU time 1.15 seconds
Started Jul 09 04:37:43 PM PDT 24
Finished Jul 09 04:37:45 PM PDT 24
Peak memory 196800 kb
Host smart-5f13cdaa-4c6c-4458-b5de-f30e08da899e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648830616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2648830616
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2711522439
Short name T655
Test name
Test status
Simulation time 31721225 ps
CPU time 0.88 seconds
Started Jul 09 04:37:42 PM PDT 24
Finished Jul 09 04:37:43 PM PDT 24
Peak memory 196064 kb
Host smart-fd192ea3-ae08-4f39-a6d1-73f5e8224a60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711522439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2711522439
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1226745025
Short name T479
Test name
Test status
Simulation time 78909529500 ps
CPU time 88.67 seconds
Started Jul 09 04:37:44 PM PDT 24
Finished Jul 09 04:39:14 PM PDT 24
Peak memory 198588 kb
Host smart-2d4514ab-3b58-4247-9117-a445128296a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226745025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1226745025
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1901208590
Short name T53
Test name
Test status
Simulation time 208563123938 ps
CPU time 2384.31 seconds
Started Jul 09 04:37:48 PM PDT 24
Finished Jul 09 05:17:34 PM PDT 24
Peak memory 198672 kb
Host smart-5b6ccb14-2700-4ff1-a3a8-f9b8bbc14eab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1901208590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1901208590
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1176542460
Short name T516
Test name
Test status
Simulation time 39080971 ps
CPU time 0.59 seconds
Started Jul 09 04:39:01 PM PDT 24
Finished Jul 09 04:39:02 PM PDT 24
Peak memory 194628 kb
Host smart-6acecd47-c9c2-4a35-8110-7cc570c16e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176542460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1176542460
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1676491015
Short name T294
Test name
Test status
Simulation time 86606710 ps
CPU time 0.74 seconds
Started Jul 09 04:39:01 PM PDT 24
Finished Jul 09 04:39:02 PM PDT 24
Peak memory 195412 kb
Host smart-6efadc87-70d1-4a06-98d7-be74d294dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676491015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1676491015
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1092169055
Short name T187
Test name
Test status
Simulation time 2880424835 ps
CPU time 22.04 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 197148 kb
Host smart-ea3720e8-eba7-488c-a061-3dee98a99e25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092169055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1092169055
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3892885803
Short name T508
Test name
Test status
Simulation time 33494719 ps
CPU time 0.69 seconds
Started Jul 09 04:39:01 PM PDT 24
Finished Jul 09 04:39:02 PM PDT 24
Peak memory 195136 kb
Host smart-14bbb56b-8d28-48e0-8899-9647b9429877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892885803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3892885803
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2291629681
Short name T313
Test name
Test status
Simulation time 110137922 ps
CPU time 1.04 seconds
Started Jul 09 04:39:01 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 196424 kb
Host smart-ce26c92d-fc4b-4a40-ac95-d8e7b1415062
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291629681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2291629681
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.864080454
Short name T683
Test name
Test status
Simulation time 279835668 ps
CPU time 2.71 seconds
Started Jul 09 04:38:59 PM PDT 24
Finished Jul 09 04:39:03 PM PDT 24
Peak memory 198536 kb
Host smart-bae94c3b-4a00-4145-bfe4-1e38aa28f571
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864080454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.864080454
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.233536580
Short name T364
Test name
Test status
Simulation time 1347306088 ps
CPU time 3.37 seconds
Started Jul 09 04:38:57 PM PDT 24
Finished Jul 09 04:39:01 PM PDT 24
Peak memory 198496 kb
Host smart-78e91e8e-2628-4880-9f69-0626e34ab8b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233536580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
233536580
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3294585717
Short name T355
Test name
Test status
Simulation time 34076869 ps
CPU time 1.21 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 197556 kb
Host smart-36034ed3-6790-444d-8684-1a785351d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294585717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3294585717
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.663482565
Short name T658
Test name
Test status
Simulation time 431084702 ps
CPU time 1.08 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 196388 kb
Host smart-4dae169e-cf04-42d2-a308-500d4e47c62b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663482565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.663482565
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4068097030
Short name T422
Test name
Test status
Simulation time 378279444 ps
CPU time 4.66 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 198520 kb
Host smart-e395ba2a-eb50-4774-9251-9ae5cee3a50a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068097030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4068097030
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3203913068
Short name T107
Test name
Test status
Simulation time 40893941 ps
CPU time 0.88 seconds
Started Jul 09 04:39:01 PM PDT 24
Finished Jul 09 04:39:03 PM PDT 24
Peak memory 195764 kb
Host smart-fb20b361-1157-4447-ae06-ce4ba2ed1558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203913068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3203913068
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4087486223
Short name T169
Test name
Test status
Simulation time 60958354 ps
CPU time 1.12 seconds
Started Jul 09 04:38:56 PM PDT 24
Finished Jul 09 04:38:58 PM PDT 24
Peak memory 196812 kb
Host smart-b03f3083-bf14-4f8f-a943-598e5ed405b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087486223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4087486223
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.717856675
Short name T326
Test name
Test status
Simulation time 8215741209 ps
CPU time 54.73 seconds
Started Jul 09 04:39:00 PM PDT 24
Finished Jul 09 04:39:56 PM PDT 24
Peak memory 198640 kb
Host smart-0d48f3da-00f3-43a5-9c6e-25bdff5b9a9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717856675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.717856675
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3435648944
Short name T480
Test name
Test status
Simulation time 13960572 ps
CPU time 0.6 seconds
Started Jul 09 04:39:05 PM PDT 24
Finished Jul 09 04:39:06 PM PDT 24
Peak memory 194440 kb
Host smart-517add1b-441d-41fe-91d1-977fc922a417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435648944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3435648944
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.301209987
Short name T544
Test name
Test status
Simulation time 130593956 ps
CPU time 0.87 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 196844 kb
Host smart-2aa8b0e6-15a8-475a-8326-8863af03639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301209987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.301209987
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2639464906
Short name T22
Test name
Test status
Simulation time 1172150519 ps
CPU time 9.41 seconds
Started Jul 09 04:38:59 PM PDT 24
Finished Jul 09 04:39:10 PM PDT 24
Peak memory 196796 kb
Host smart-c5df57c2-97ed-46a9-ad80-8ef27a678a7e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639464906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2639464906
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1469342729
Short name T473
Test name
Test status
Simulation time 54886712 ps
CPU time 0.93 seconds
Started Jul 09 04:39:00 PM PDT 24
Finished Jul 09 04:39:02 PM PDT 24
Peak memory 197696 kb
Host smart-99b8d0dd-237e-4dd0-88e2-268dd4cf078e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469342729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1469342729
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1268912525
Short name T476
Test name
Test status
Simulation time 57330542 ps
CPU time 0.95 seconds
Started Jul 09 04:39:03 PM PDT 24
Finished Jul 09 04:39:06 PM PDT 24
Peak memory 196544 kb
Host smart-d7aec888-d4a1-4738-83a9-f4f8282cda5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268912525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1268912525
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4028946337
Short name T517
Test name
Test status
Simulation time 95570700 ps
CPU time 3.14 seconds
Started Jul 09 04:39:01 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 198728 kb
Host smart-29f90dd5-8591-4d7c-a8fb-94afda2e3e69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028946337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4028946337
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.924239163
Short name T302
Test name
Test status
Simulation time 227062968 ps
CPU time 2.21 seconds
Started Jul 09 04:39:00 PM PDT 24
Finished Jul 09 04:39:03 PM PDT 24
Peak memory 198616 kb
Host smart-d0cb547e-ca80-4854-8ad5-3beff801692a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924239163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
924239163
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2203232544
Short name T188
Test name
Test status
Simulation time 98260008 ps
CPU time 0.81 seconds
Started Jul 09 04:39:01 PM PDT 24
Finished Jul 09 04:39:03 PM PDT 24
Peak memory 196000 kb
Host smart-bc9b8101-2ad1-43f0-a25e-7c441ba20324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203232544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2203232544
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3822807333
Short name T331
Test name
Test status
Simulation time 339938667 ps
CPU time 0.79 seconds
Started Jul 09 04:38:58 PM PDT 24
Finished Jul 09 04:38:59 PM PDT 24
Peak memory 197112 kb
Host smart-a001b5f6-0be6-4322-9d13-e64c8f0daab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822807333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3822807333
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1093669782
Short name T686
Test name
Test status
Simulation time 738670814 ps
CPU time 3.69 seconds
Started Jul 09 04:38:59 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 198468 kb
Host smart-9f8b8f74-21d1-4967-8094-d2488a0d5938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093669782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1093669782
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1805224401
Short name T378
Test name
Test status
Simulation time 147501246 ps
CPU time 0.93 seconds
Started Jul 09 04:39:00 PM PDT 24
Finished Jul 09 04:39:02 PM PDT 24
Peak memory 195972 kb
Host smart-731ab5ae-d31e-42a5-8a68-4a4ca53ec066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805224401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1805224401
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.901926453
Short name T220
Test name
Test status
Simulation time 43727794 ps
CPU time 1.27 seconds
Started Jul 09 04:38:59 PM PDT 24
Finished Jul 09 04:39:02 PM PDT 24
Peak memory 196292 kb
Host smart-d007fd4e-5c27-4278-a137-084fd9db93ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901926453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.901926453
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2306002667
Short name T282
Test name
Test status
Simulation time 36400243272 ps
CPU time 136.9 seconds
Started Jul 09 04:39:06 PM PDT 24
Finished Jul 09 04:41:23 PM PDT 24
Peak memory 198760 kb
Host smart-a0428dc3-ac11-41d3-bb24-22de9729e143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306002667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2306002667
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2341154959
Short name T598
Test name
Test status
Simulation time 42060616 ps
CPU time 0.57 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:03 PM PDT 24
Peak memory 195212 kb
Host smart-6278a1c2-6e08-425d-8b39-42bdbac4dd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341154959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2341154959
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2539182013
Short name T362
Test name
Test status
Simulation time 90758066 ps
CPU time 0.72 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:08 PM PDT 24
Peak memory 194936 kb
Host smart-ad46ec58-9059-4005-aca7-9250820ba846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539182013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2539182013
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1521401215
Short name T239
Test name
Test status
Simulation time 366873065 ps
CPU time 6.2 seconds
Started Jul 09 04:39:03 PM PDT 24
Finished Jul 09 04:39:11 PM PDT 24
Peak memory 197360 kb
Host smart-0b2ceedc-1bf4-4575-97dc-60e695950317
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521401215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1521401215
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1945102658
Short name T199
Test name
Test status
Simulation time 80862280 ps
CPU time 0.67 seconds
Started Jul 09 04:39:06 PM PDT 24
Finished Jul 09 04:39:07 PM PDT 24
Peak memory 195460 kb
Host smart-2dcf7c7f-41c6-466f-963e-c935eabdb2ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945102658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1945102658
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1935077861
Short name T159
Test name
Test status
Simulation time 60050848 ps
CPU time 1 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 197048 kb
Host smart-bc1e91d9-471b-472d-b140-c6a56a227fb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935077861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1935077861
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1000190655
Short name T346
Test name
Test status
Simulation time 265320680 ps
CPU time 1.59 seconds
Started Jul 09 04:39:03 PM PDT 24
Finished Jul 09 04:39:07 PM PDT 24
Peak memory 197224 kb
Host smart-ce5ab058-f93c-4462-a870-a4390ee5287c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000190655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1000190655
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1760271599
Short name T149
Test name
Test status
Simulation time 28039773 ps
CPU time 0.92 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 195752 kb
Host smart-cd22a78d-ae45-4d37-84b8-933f4d6f368e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760271599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1760271599
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.524933532
Short name T716
Test name
Test status
Simulation time 66294225 ps
CPU time 0.84 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 197292 kb
Host smart-a81678d4-21b9-4774-82b3-d488cf7d1535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524933532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.524933532
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.156377735
Short name T234
Test name
Test status
Simulation time 135694664 ps
CPU time 1.35 seconds
Started Jul 09 04:39:03 PM PDT 24
Finished Jul 09 04:39:06 PM PDT 24
Peak memory 196972 kb
Host smart-d7bfa563-dbb7-4c54-bf1a-53afc708d7e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156377735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.156377735
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2656822967
Short name T512
Test name
Test status
Simulation time 794983052 ps
CPU time 4.7 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 198548 kb
Host smart-07e9d88a-3a05-4fdc-bcbf-cd3786af3ed2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656822967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2656822967
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.4176042801
Short name T685
Test name
Test status
Simulation time 117222696 ps
CPU time 1.18 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:06 PM PDT 24
Peak memory 196120 kb
Host smart-029d4d50-1a6a-4fb7-afee-6cd03a08516d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176042801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.4176042801
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2580942611
Short name T257
Test name
Test status
Simulation time 77998023 ps
CPU time 1.31 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:06 PM PDT 24
Peak memory 196804 kb
Host smart-4aecf489-d67e-4525-b999-b193c13b7771
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580942611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2580942611
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3774881045
Short name T361
Test name
Test status
Simulation time 7243265071 ps
CPU time 103.98 seconds
Started Jul 09 04:39:03 PM PDT 24
Finished Jul 09 04:40:49 PM PDT 24
Peak memory 198648 kb
Host smart-d71f7033-98a7-4e9b-a698-d59a017b4f27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774881045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3774881045
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3638148324
Short name T97
Test name
Test status
Simulation time 109906224267 ps
CPU time 894.07 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:53:59 PM PDT 24
Peak memory 198756 kb
Host smart-b8859465-b8ba-41ad-9b34-344543e9c24a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3638148324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3638148324
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3131582484
Short name T493
Test name
Test status
Simulation time 153501881 ps
CPU time 0.62 seconds
Started Jul 09 04:39:08 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 194516 kb
Host smart-538b8e14-9421-4c47-b355-8a2ca79355b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131582484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3131582484
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4186475050
Short name T144
Test name
Test status
Simulation time 321920024 ps
CPU time 0.81 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:08 PM PDT 24
Peak memory 196640 kb
Host smart-4f740afd-5214-494e-b35b-d2c6a1382514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186475050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4186475050
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2670930329
Short name T115
Test name
Test status
Simulation time 2401672656 ps
CPU time 19.58 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 198000 kb
Host smart-b56816ef-2f23-4669-9fc7-195cce17613f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670930329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2670930329
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.326965152
Short name T415
Test name
Test status
Simulation time 51705884 ps
CPU time 0.82 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 196456 kb
Host smart-bccc47ef-f19d-4ff4-89e0-82b669ceefd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326965152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.326965152
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4247794452
Short name T394
Test name
Test status
Simulation time 35680259 ps
CPU time 1.06 seconds
Started Jul 09 04:39:05 PM PDT 24
Finished Jul 09 04:39:07 PM PDT 24
Peak memory 196660 kb
Host smart-f8f1f5f5-d5c7-4b52-aa98-b92aceca753d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247794452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4247794452
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.488540538
Short name T370
Test name
Test status
Simulation time 133116898 ps
CPU time 0.88 seconds
Started Jul 09 04:39:03 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 196724 kb
Host smart-de16fbc8-a936-4bf7-9f94-d780ef97a055
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488540538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.488540538
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2154689803
Short name T200
Test name
Test status
Simulation time 47782145 ps
CPU time 1.29 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 197384 kb
Host smart-294e2b56-a621-46d4-8846-7c461aef8698
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154689803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2154689803
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2083504971
Short name T277
Test name
Test status
Simulation time 13395459 ps
CPU time 0.64 seconds
Started Jul 09 04:39:06 PM PDT 24
Finished Jul 09 04:39:07 PM PDT 24
Peak memory 194872 kb
Host smart-01228b0b-44ff-42ee-8b82-db9228157da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083504971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2083504971
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3815387526
Short name T215
Test name
Test status
Simulation time 57183425 ps
CPU time 0.69 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 194860 kb
Host smart-567f98d4-82df-471c-a5e5-d7a630db74ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815387526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3815387526
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3226628941
Short name T4
Test name
Test status
Simulation time 219049596 ps
CPU time 2.8 seconds
Started Jul 09 04:39:06 PM PDT 24
Finished Jul 09 04:39:10 PM PDT 24
Peak memory 198896 kb
Host smart-a61d5615-2583-486f-b18d-60cab248a435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226628941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3226628941
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1214804077
Short name T128
Test name
Test status
Simulation time 86811805 ps
CPU time 1.08 seconds
Started Jul 09 04:39:02 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 197076 kb
Host smart-994b6e21-1801-488a-b6ec-f3a84ef93a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214804077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1214804077
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.4195954314
Short name T121
Test name
Test status
Simulation time 67879846 ps
CPU time 1.19 seconds
Started Jul 09 04:39:05 PM PDT 24
Finished Jul 09 04:39:07 PM PDT 24
Peak memory 196948 kb
Host smart-f0a9e458-4ffa-40e4-8e8c-32c1bc281066
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195954314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.4195954314
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.60570933
Short name T357
Test name
Test status
Simulation time 31461083581 ps
CPU time 199.45 seconds
Started Jul 09 04:39:03 PM PDT 24
Finished Jul 09 04:42:25 PM PDT 24
Peak memory 198696 kb
Host smart-b25db8aa-51f2-41d8-919f-b4c8a49fcb57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60570933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gp
io_stress_all.60570933
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.664359077
Short name T154
Test name
Test status
Simulation time 15105226 ps
CPU time 0.57 seconds
Started Jul 09 04:39:10 PM PDT 24
Finished Jul 09 04:39:11 PM PDT 24
Peak memory 195084 kb
Host smart-b386ff88-0048-49f6-9c3d-42e545586cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664359077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.664359077
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.983153177
Short name T143
Test name
Test status
Simulation time 32287092 ps
CPU time 0.72 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 195828 kb
Host smart-693e8adc-432f-4197-ab6a-2fb92b6ca14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983153177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.983153177
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2248039623
Short name T397
Test name
Test status
Simulation time 80536523 ps
CPU time 3.78 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:11 PM PDT 24
Peak memory 196516 kb
Host smart-29430b21-eaee-41c4-98a6-f81fec860c55
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248039623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2248039623
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2975083101
Short name T350
Test name
Test status
Simulation time 58278804 ps
CPU time 0.84 seconds
Started Jul 09 04:39:09 PM PDT 24
Finished Jul 09 04:39:10 PM PDT 24
Peak memory 197232 kb
Host smart-5a14b9da-ae2b-4087-8842-1e2d2ed53e15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975083101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2975083101
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1879257614
Short name T152
Test name
Test status
Simulation time 337205741 ps
CPU time 0.81 seconds
Started Jul 09 04:39:06 PM PDT 24
Finished Jul 09 04:39:07 PM PDT 24
Peak memory 196076 kb
Host smart-61dc0d9f-e86f-45e5-ae17-a9a895552e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879257614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1879257614
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3283186225
Short name T206
Test name
Test status
Simulation time 245629708 ps
CPU time 2.49 seconds
Started Jul 09 04:39:06 PM PDT 24
Finished Jul 09 04:39:10 PM PDT 24
Peak memory 198608 kb
Host smart-8f020273-6c25-4c83-9837-a58b977febac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283186225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3283186225
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2490308838
Short name T340
Test name
Test status
Simulation time 121903143 ps
CPU time 3.02 seconds
Started Jul 09 04:39:08 PM PDT 24
Finished Jul 09 04:39:12 PM PDT 24
Peak memory 197704 kb
Host smart-5cd51395-65e5-4f86-8963-7ae12030453b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490308838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2490308838
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2566990411
Short name T676
Test name
Test status
Simulation time 43506527 ps
CPU time 1.01 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 196524 kb
Host smart-370f8d17-0d4c-44cb-aa84-6f458ebac13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566990411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2566990411
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2142704434
Short name T321
Test name
Test status
Simulation time 71461908 ps
CPU time 0.94 seconds
Started Jul 09 04:39:06 PM PDT 24
Finished Jul 09 04:39:08 PM PDT 24
Peak memory 196428 kb
Host smart-c8c0316f-f91c-4885-9dee-d5a47da8529b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142704434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2142704434
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1629504699
Short name T596
Test name
Test status
Simulation time 467814507 ps
CPU time 4.56 seconds
Started Jul 09 04:39:08 PM PDT 24
Finished Jul 09 04:39:13 PM PDT 24
Peak memory 198488 kb
Host smart-e0b1b0ba-c190-416e-94cc-27e6d7c8dcf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629504699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1629504699
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.174145707
Short name T406
Test name
Test status
Simulation time 80006781 ps
CPU time 1.31 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 196220 kb
Host smart-136d949f-1ddc-4e7f-91c7-0bde4a35028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174145707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.174145707
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.308570489
Short name T500
Test name
Test status
Simulation time 383255297 ps
CPU time 1.06 seconds
Started Jul 09 04:39:08 PM PDT 24
Finished Jul 09 04:39:10 PM PDT 24
Peak memory 196380 kb
Host smart-cda41a0f-91e5-4468-835a-840b58d89f55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308570489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.308570489
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2740999582
Short name T699
Test name
Test status
Simulation time 111378459070 ps
CPU time 139.31 seconds
Started Jul 09 04:39:11 PM PDT 24
Finished Jul 09 04:41:31 PM PDT 24
Peak memory 198492 kb
Host smart-30371692-11ee-4026-acc8-581c6a757b6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740999582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2740999582
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3794133774
Short name T98
Test name
Test status
Simulation time 320760984473 ps
CPU time 551.91 seconds
Started Jul 09 04:39:11 PM PDT 24
Finished Jul 09 04:48:24 PM PDT 24
Peak memory 206952 kb
Host smart-a84a598f-af1c-45c3-999f-f06f08ebece5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3794133774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3794133774
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3960341787
Short name T429
Test name
Test status
Simulation time 37673811 ps
CPU time 0.62 seconds
Started Jul 09 04:39:11 PM PDT 24
Finished Jul 09 04:39:12 PM PDT 24
Peak memory 195372 kb
Host smart-d3c58aec-0c26-4de5-9efe-4897f94c9cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960341787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3960341787
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3747369868
Short name T555
Test name
Test status
Simulation time 26789007 ps
CPU time 0.8 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 195988 kb
Host smart-3619a224-c433-4ac1-bccb-8be568c13b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747369868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3747369868
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4274011940
Short name T637
Test name
Test status
Simulation time 1153048654 ps
CPU time 3.64 seconds
Started Jul 09 04:39:13 PM PDT 24
Finished Jul 09 04:39:18 PM PDT 24
Peak memory 196500 kb
Host smart-7b7a274e-7fbf-4009-943b-23f6fc70227e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274011940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4274011940
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1788886196
Short name T462
Test name
Test status
Simulation time 385137784 ps
CPU time 0.89 seconds
Started Jul 09 04:39:12 PM PDT 24
Finished Jul 09 04:39:14 PM PDT 24
Peak memory 197320 kb
Host smart-67bd9fab-bfc3-4cf8-a18b-de63a4229bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788886196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1788886196
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2972960040
Short name T463
Test name
Test status
Simulation time 32530719 ps
CPU time 0.94 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 196284 kb
Host smart-b9e52e4c-040c-4d1b-b520-85e89fb2a233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972960040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2972960040
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.916788580
Short name T309
Test name
Test status
Simulation time 185425115 ps
CPU time 3.72 seconds
Started Jul 09 04:39:15 PM PDT 24
Finished Jul 09 04:39:19 PM PDT 24
Peak memory 198620 kb
Host smart-c001a948-6947-4f79-8205-40aaf1a214ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916788580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.916788580
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2183148346
Short name T660
Test name
Test status
Simulation time 495060346 ps
CPU time 2.52 seconds
Started Jul 09 04:39:13 PM PDT 24
Finished Jul 09 04:39:16 PM PDT 24
Peak memory 197728 kb
Host smart-0fd3d13c-77ae-4e74-be27-81a005372e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183148346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2183148346
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3153396705
Short name T384
Test name
Test status
Simulation time 44398685 ps
CPU time 0.96 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 196588 kb
Host smart-3e6117c0-298c-4981-a002-b1de22f8e3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153396705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3153396705
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3020466933
Short name T240
Test name
Test status
Simulation time 194635019 ps
CPU time 1.17 seconds
Started Jul 09 04:39:09 PM PDT 24
Finished Jul 09 04:39:10 PM PDT 24
Peak memory 197088 kb
Host smart-4c73d2d4-7590-412e-b1b7-363d5ba083f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020466933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3020466933
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.71213309
Short name T501
Test name
Test status
Simulation time 2109597587 ps
CPU time 5 seconds
Started Jul 09 04:39:13 PM PDT 24
Finished Jul 09 04:39:18 PM PDT 24
Peak memory 198492 kb
Host smart-50aca05a-dab6-4590-bf3c-c2ab3e89b58d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71213309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand
om_long_reg_writes_reg_reads.71213309
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.503957052
Short name T687
Test name
Test status
Simulation time 364280820 ps
CPU time 1.5 seconds
Started Jul 09 04:39:10 PM PDT 24
Finished Jul 09 04:39:13 PM PDT 24
Peak memory 196072 kb
Host smart-5b12c660-ed0c-47de-9a58-a1d80827307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503957052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.503957052
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3485203473
Short name T261
Test name
Test status
Simulation time 34531823 ps
CPU time 1.05 seconds
Started Jul 09 04:39:07 PM PDT 24
Finished Jul 09 04:39:09 PM PDT 24
Peak memory 197016 kb
Host smart-b34b0f9b-396c-4e8e-a122-e849b140a2cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485203473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3485203473
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3614320619
Short name T519
Test name
Test status
Simulation time 15416349560 ps
CPU time 151.14 seconds
Started Jul 09 04:39:13 PM PDT 24
Finished Jul 09 04:41:45 PM PDT 24
Peak memory 198676 kb
Host smart-4663c66c-71e7-480f-873c-93db6cdfa99f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614320619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3614320619
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2785768837
Short name T698
Test name
Test status
Simulation time 21640751 ps
CPU time 0.56 seconds
Started Jul 09 04:39:14 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 194548 kb
Host smart-a90d6478-aa89-4b7d-8564-10490b330b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785768837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2785768837
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3288222886
Short name T668
Test name
Test status
Simulation time 41178940 ps
CPU time 0.73 seconds
Started Jul 09 04:39:11 PM PDT 24
Finished Jul 09 04:39:13 PM PDT 24
Peak memory 195804 kb
Host smart-3a37baac-a89d-4a89-b2ed-45b0220e9e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288222886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3288222886
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3588734822
Short name T360
Test name
Test status
Simulation time 119841096 ps
CPU time 5.86 seconds
Started Jul 09 04:39:15 PM PDT 24
Finished Jul 09 04:39:21 PM PDT 24
Peak memory 197372 kb
Host smart-4dad6977-a650-40c0-82f6-614454421603
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588734822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3588734822
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4052917821
Short name T120
Test name
Test status
Simulation time 91734713 ps
CPU time 1.07 seconds
Started Jul 09 04:39:14 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 197192 kb
Host smart-eeb9841e-df91-43a5-9709-5fee5eee42d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052917821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4052917821
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.4292114777
Short name T530
Test name
Test status
Simulation time 63415182 ps
CPU time 1.05 seconds
Started Jul 09 04:39:10 PM PDT 24
Finished Jul 09 04:39:12 PM PDT 24
Peak memory 196320 kb
Host smart-5508a25a-ed98-42ba-80bf-0481dcc5b0cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292114777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.4292114777
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1243634087
Short name T404
Test name
Test status
Simulation time 313896128 ps
CPU time 3.01 seconds
Started Jul 09 04:39:14 PM PDT 24
Finished Jul 09 04:39:18 PM PDT 24
Peak memory 198560 kb
Host smart-022673f2-f679-4033-b61a-f5295b5f7595
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243634087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1243634087
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1013609601
Short name T114
Test name
Test status
Simulation time 201392762 ps
CPU time 2.06 seconds
Started Jul 09 04:39:12 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 196764 kb
Host smart-36107dd9-b5f4-4516-8c32-b8401e0bfcd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013609601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1013609601
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3042368078
Short name T638
Test name
Test status
Simulation time 156365532 ps
CPU time 1.28 seconds
Started Jul 09 04:39:13 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 197172 kb
Host smart-f44c274b-ba42-401b-aebc-30ac0d2be753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042368078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3042368078
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3192221496
Short name T466
Test name
Test status
Simulation time 78734420 ps
CPU time 1.09 seconds
Started Jul 09 04:39:11 PM PDT 24
Finished Jul 09 04:39:13 PM PDT 24
Peak memory 196632 kb
Host smart-038c6108-4f08-4977-8008-1cfc8f755086
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192221496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3192221496
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1149335253
Short name T20
Test name
Test status
Simulation time 467202590 ps
CPU time 6.08 seconds
Started Jul 09 04:39:12 PM PDT 24
Finished Jul 09 04:39:19 PM PDT 24
Peak memory 198360 kb
Host smart-94924db9-88ce-45e6-abab-a5c1bd844fe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149335253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1149335253
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3162485432
Short name T183
Test name
Test status
Simulation time 135329186 ps
CPU time 1.34 seconds
Started Jul 09 04:39:14 PM PDT 24
Finished Jul 09 04:39:16 PM PDT 24
Peak memory 196784 kb
Host smart-326fa8c4-c81d-4584-9ff3-0d881cb6dccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162485432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3162485432
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3042559766
Short name T452
Test name
Test status
Simulation time 120504507 ps
CPU time 1.08 seconds
Started Jul 09 04:39:16 PM PDT 24
Finished Jul 09 04:39:17 PM PDT 24
Peak memory 196120 kb
Host smart-7372cc76-6949-46f3-b1a8-83fc2894b683
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042559766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3042559766
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3497695782
Short name T679
Test name
Test status
Simulation time 29658719087 ps
CPU time 54.5 seconds
Started Jul 09 04:39:14 PM PDT 24
Finished Jul 09 04:40:09 PM PDT 24
Peak memory 198700 kb
Host smart-f86029b5-a22a-4c73-9b13-454b376635a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497695782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3497695782
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3318959326
Short name T310
Test name
Test status
Simulation time 12977417 ps
CPU time 0.59 seconds
Started Jul 09 04:39:20 PM PDT 24
Finished Jul 09 04:39:21 PM PDT 24
Peak memory 195412 kb
Host smart-c69b39c8-3959-475f-8fb7-52212bcf94eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318959326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3318959326
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3862976989
Short name T552
Test name
Test status
Simulation time 60487905 ps
CPU time 0.77 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:21 PM PDT 24
Peak memory 195824 kb
Host smart-a2a0b837-d4e4-4a8d-ad62-8b4e8e2e8f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862976989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3862976989
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.706937362
Short name T238
Test name
Test status
Simulation time 200515785 ps
CPU time 11.19 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 04:39:37 PM PDT 24
Peak memory 197564 kb
Host smart-6b5fabad-cccc-4a9c-9f7e-a681e37c1148
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706937362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.706937362
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.776831088
Short name T661
Test name
Test status
Simulation time 67280614 ps
CPU time 0.86 seconds
Started Jul 09 04:39:17 PM PDT 24
Finished Jul 09 04:39:19 PM PDT 24
Peak memory 196412 kb
Host smart-4f9ef8fc-01fd-4b71-8625-a814a7f6e438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776831088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.776831088
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2294778070
Short name T276
Test name
Test status
Simulation time 99978949 ps
CPU time 0.71 seconds
Started Jul 09 04:39:18 PM PDT 24
Finished Jul 09 04:39:20 PM PDT 24
Peak memory 195992 kb
Host smart-1fc05c1f-f7f8-4e35-ad70-19f34865b097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294778070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2294778070
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1739543982
Short name T693
Test name
Test status
Simulation time 366769113 ps
CPU time 2.41 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:23 PM PDT 24
Peak memory 198568 kb
Host smart-ea252766-3710-4978-b6d4-eb1efcc8f1db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739543982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1739543982
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2597559856
Short name T312
Test name
Test status
Simulation time 1523722532 ps
CPU time 2.71 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 198512 kb
Host smart-4a0a31b1-018d-4ca5-b46f-61ffbc4ba8dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597559856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2597559856
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.996788980
Short name T489
Test name
Test status
Simulation time 25761936 ps
CPU time 0.88 seconds
Started Jul 09 04:39:12 PM PDT 24
Finished Jul 09 04:39:13 PM PDT 24
Peak memory 196496 kb
Host smart-80179e97-7e4c-4641-9f58-6b019443e2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996788980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.996788980
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3478290665
Short name T126
Test name
Test status
Simulation time 45413771 ps
CPU time 0.99 seconds
Started Jul 09 04:39:21 PM PDT 24
Finished Jul 09 04:39:22 PM PDT 24
Peak memory 197300 kb
Host smart-45691085-2094-40b5-84c9-571ec6cebf14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478290665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3478290665
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2700772243
Short name T483
Test name
Test status
Simulation time 448379637 ps
CPU time 1.49 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 196860 kb
Host smart-9914d318-a116-4f6e-a5b4-b2ac9e2896bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700772243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2700772243
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3729844576
Short name T612
Test name
Test status
Simulation time 47010763 ps
CPU time 0.84 seconds
Started Jul 09 04:39:14 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 197660 kb
Host smart-094c1f8f-7ba4-4617-bb1f-c7ec7a07cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729844576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3729844576
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.103906317
Short name T289
Test name
Test status
Simulation time 203972096 ps
CPU time 1.14 seconds
Started Jul 09 04:39:12 PM PDT 24
Finished Jul 09 04:39:14 PM PDT 24
Peak memory 196268 kb
Host smart-b071248d-5793-45f4-bfac-f525063d3dba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103906317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.103906317
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.4138741279
Short name T211
Test name
Test status
Simulation time 9197685063 ps
CPU time 61.09 seconds
Started Jul 09 04:39:16 PM PDT 24
Finished Jul 09 04:40:18 PM PDT 24
Peak memory 198612 kb
Host smart-e5aa397e-bc8b-4bd0-9f50-d1a8341743a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138741279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.4138741279
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2250945883
Short name T456
Test name
Test status
Simulation time 12909375 ps
CPU time 0.57 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 195220 kb
Host smart-25009aed-7588-4482-bfdd-a256e8faf850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250945883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2250945883
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.725327554
Short name T217
Test name
Test status
Simulation time 44042464 ps
CPU time 0.62 seconds
Started Jul 09 04:39:16 PM PDT 24
Finished Jul 09 04:39:17 PM PDT 24
Peak memory 194676 kb
Host smart-faecff05-dfd0-4b6d-991f-6028f40c5d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725327554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.725327554
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.183863445
Short name T221
Test name
Test status
Simulation time 229054581 ps
CPU time 10.57 seconds
Started Jul 09 04:39:18 PM PDT 24
Finished Jul 09 04:39:29 PM PDT 24
Peak memory 197396 kb
Host smart-11a30bdc-edbb-4f61-bd41-355facbf94ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183863445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.183863445
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1969217380
Short name T449
Test name
Test status
Simulation time 165491877 ps
CPU time 0.8 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 196444 kb
Host smart-9fdb4215-29ef-4068-bd28-329af235536e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969217380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1969217380
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3290117307
Short name T542
Test name
Test status
Simulation time 91807636 ps
CPU time 1.3 seconds
Started Jul 09 04:39:17 PM PDT 24
Finished Jul 09 04:39:19 PM PDT 24
Peak memory 196624 kb
Host smart-5e5f670c-9b50-466a-9510-ccda754a8fe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290117307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3290117307
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2125498306
Short name T371
Test name
Test status
Simulation time 138457068 ps
CPU time 2.95 seconds
Started Jul 09 04:39:20 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 198496 kb
Host smart-8690818b-6ce6-4b9a-b75a-4a2e09e8da0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125498306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2125498306
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1442741509
Short name T439
Test name
Test status
Simulation time 116185919 ps
CPU time 2.41 seconds
Started Jul 09 04:39:20 PM PDT 24
Finished Jul 09 04:39:23 PM PDT 24
Peak memory 197716 kb
Host smart-23f3851a-159d-4bae-9915-f5074ddcf90f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442741509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1442741509
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4230838863
Short name T525
Test name
Test status
Simulation time 22207103 ps
CPU time 0.85 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:25 PM PDT 24
Peak memory 197908 kb
Host smart-2e89c851-2fb8-4ea0-b7c0-66423a7171b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230838863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4230838863
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2714615984
Short name T532
Test name
Test status
Simulation time 157699250 ps
CPU time 1.05 seconds
Started Jul 09 04:39:17 PM PDT 24
Finished Jul 09 04:39:18 PM PDT 24
Peak memory 196688 kb
Host smart-112631af-c29c-41ee-8179-2726edbbe4e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714615984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2714615984
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2388278577
Short name T252
Test name
Test status
Simulation time 73535362 ps
CPU time 3.2 seconds
Started Jul 09 04:39:20 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 198616 kb
Host smart-f414abca-4386-4d4a-a1d0-bf085af1e844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388278577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2388278577
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1746070010
Short name T303
Test name
Test status
Simulation time 79178239 ps
CPU time 1.37 seconds
Started Jul 09 04:39:16 PM PDT 24
Finished Jul 09 04:39:18 PM PDT 24
Peak memory 196152 kb
Host smart-9bc6fca1-fb34-4694-9d4c-61213b00921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746070010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1746070010
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2523689552
Short name T535
Test name
Test status
Simulation time 55690504 ps
CPU time 0.94 seconds
Started Jul 09 04:39:18 PM PDT 24
Finished Jul 09 04:39:19 PM PDT 24
Peak memory 196376 kb
Host smart-abbd8b02-7dae-4ff7-a9bf-fa371345f9f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523689552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2523689552
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.373074951
Short name T327
Test name
Test status
Simulation time 31971566233 ps
CPU time 119.08 seconds
Started Jul 09 04:39:18 PM PDT 24
Finished Jul 09 04:41:18 PM PDT 24
Peak memory 198732 kb
Host smart-ad99bb15-0e1a-41f0-86b8-98c576a70b69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373074951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.373074951
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2885478225
Short name T645
Test name
Test status
Simulation time 14082415 ps
CPU time 0.58 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 195164 kb
Host smart-7509b786-5fa6-44f1-8d67-ea66accab7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885478225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2885478225
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2617898219
Short name T292
Test name
Test status
Simulation time 79004123 ps
CPU time 0.86 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:21 PM PDT 24
Peak memory 197124 kb
Host smart-99215233-978a-4820-8b8c-0d790888cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617898219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2617898219
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2478148167
Short name T40
Test name
Test status
Simulation time 716785427 ps
CPU time 19.08 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 197564 kb
Host smart-53c07099-e423-46f0-bea9-988a752e5894
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478148167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2478148167
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2438689242
Short name T5
Test name
Test status
Simulation time 191486898 ps
CPU time 0.79 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:20 PM PDT 24
Peak memory 196448 kb
Host smart-cc521348-c99f-4ec1-99cd-3857f7b32a23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438689242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2438689242
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3134339743
Short name T575
Test name
Test status
Simulation time 85075158 ps
CPU time 1.37 seconds
Started Jul 09 04:39:23 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 197444 kb
Host smart-a4917381-0099-4d4f-b3df-67d1f39a9f6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134339743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3134339743
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.476184907
Short name T191
Test name
Test status
Simulation time 124785088 ps
CPU time 2.37 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 197836 kb
Host smart-917b112c-a4a3-4e90-9c9e-3a633b5df8e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476184907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.476184907
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1594335487
Short name T198
Test name
Test status
Simulation time 337145737 ps
CPU time 3.01 seconds
Started Jul 09 04:39:21 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 197688 kb
Host smart-1b8130fe-5333-484e-a745-51e606b8d09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594335487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1594335487
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3522367713
Short name T305
Test name
Test status
Simulation time 55762298 ps
CPU time 1.11 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 196680 kb
Host smart-6cb2d2e4-d0fa-44c3-bf7f-db4bf54fb5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522367713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3522367713
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2891391367
Short name T403
Test name
Test status
Simulation time 22302902 ps
CPU time 0.93 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:21 PM PDT 24
Peak memory 197280 kb
Host smart-bcffc511-fb81-4282-b856-3b60a47821ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891391367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2891391367
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3591873217
Short name T91
Test name
Test status
Simulation time 228930020 ps
CPU time 5.57 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:27 PM PDT 24
Peak memory 198832 kb
Host smart-f9d88221-0c82-4875-be53-43c68bd00abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591873217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3591873217
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2638688288
Short name T502
Test name
Test status
Simulation time 39534725 ps
CPU time 1.19 seconds
Started Jul 09 04:39:26 PM PDT 24
Finished Jul 09 04:39:28 PM PDT 24
Peak memory 197428 kb
Host smart-3280e395-3e09-40cc-919e-b9c885468063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638688288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2638688288
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3252353800
Short name T141
Test name
Test status
Simulation time 71243689 ps
CPU time 0.84 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:21 PM PDT 24
Peak memory 195680 kb
Host smart-89c0ac3e-5af4-42d0-a21a-6556387c3262
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252353800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3252353800
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3352851672
Short name T243
Test name
Test status
Simulation time 4236857146 ps
CPU time 107.43 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:41:07 PM PDT 24
Peak memory 198668 kb
Host smart-b46fffd3-a574-4a92-84b6-9d093ae634a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352851672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3352851672
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2022997478
Short name T472
Test name
Test status
Simulation time 49992147149 ps
CPU time 382.83 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:45:50 PM PDT 24
Peak memory 198772 kb
Host smart-287fc3d0-e390-4ecb-a7c6-7ce4651cbb29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2022997478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2022997478
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3529290780
Short name T338
Test name
Test status
Simulation time 27964674 ps
CPU time 0.55 seconds
Started Jul 09 04:37:55 PM PDT 24
Finished Jul 09 04:37:57 PM PDT 24
Peak memory 194576 kb
Host smart-22fdbcc2-69f2-4a8a-9f22-44690f0733c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529290780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3529290780
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1820098822
Short name T713
Test name
Test status
Simulation time 29491733 ps
CPU time 0.78 seconds
Started Jul 09 04:37:49 PM PDT 24
Finished Jul 09 04:37:51 PM PDT 24
Peak memory 195932 kb
Host smart-c68c263c-bae0-433b-a94c-b0fe207100a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820098822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1820098822
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2671186156
Short name T579
Test name
Test status
Simulation time 795207383 ps
CPU time 22.47 seconds
Started Jul 09 04:37:51 PM PDT 24
Finished Jul 09 04:38:15 PM PDT 24
Peak memory 196016 kb
Host smart-5f6d80ff-080a-4c14-878d-c084f92825a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671186156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2671186156
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.218014988
Short name T377
Test name
Test status
Simulation time 143475114 ps
CPU time 0.99 seconds
Started Jul 09 04:37:54 PM PDT 24
Finished Jul 09 04:37:56 PM PDT 24
Peak memory 198284 kb
Host smart-290f10a1-57a8-4a63-8321-b9d90bc46636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218014988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.218014988
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2514126693
Short name T203
Test name
Test status
Simulation time 38801766 ps
CPU time 0.98 seconds
Started Jul 09 04:37:49 PM PDT 24
Finished Jul 09 04:37:52 PM PDT 24
Peak memory 196484 kb
Host smart-636dcabf-1ba7-4b00-a792-90817c3ab876
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514126693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2514126693
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.547791124
Short name T270
Test name
Test status
Simulation time 89997191 ps
CPU time 3.31 seconds
Started Jul 09 04:37:52 PM PDT 24
Finished Jul 09 04:37:56 PM PDT 24
Peak memory 198712 kb
Host smart-c5a250aa-4c9f-4199-bbea-6157147f72a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547791124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.547791124
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.246888564
Short name T122
Test name
Test status
Simulation time 237921561 ps
CPU time 2.29 seconds
Started Jul 09 04:37:51 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 198644 kb
Host smart-3a94709f-20b6-4c30-9c5b-692563219db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246888564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.246888564
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.481661537
Short name T17
Test name
Test status
Simulation time 35823822 ps
CPU time 1.2 seconds
Started Jul 09 04:37:48 PM PDT 24
Finished Jul 09 04:37:51 PM PDT 24
Peak memory 197392 kb
Host smart-7a21455e-580b-4ad4-bb62-e95c4df24545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481661537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.481661537
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3493590910
Short name T306
Test name
Test status
Simulation time 60172833 ps
CPU time 0.72 seconds
Started Jul 09 04:37:48 PM PDT 24
Finished Jul 09 04:37:50 PM PDT 24
Peak memory 196068 kb
Host smart-ac4950bd-a1af-458d-bec6-7ca0c9040455
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493590910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3493590910
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2498975501
Short name T161
Test name
Test status
Simulation time 1215320694 ps
CPU time 4.54 seconds
Started Jul 09 04:37:55 PM PDT 24
Finished Jul 09 04:38:00 PM PDT 24
Peak memory 198488 kb
Host smart-b9fb41c3-6a8b-4f78-a9b8-0da79546d080
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498975501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2498975501
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1810767410
Short name T30
Test name
Test status
Simulation time 145728235 ps
CPU time 0.76 seconds
Started Jul 09 04:37:53 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 214224 kb
Host smart-830dbc44-b0e2-4dc1-811b-a3097a983e4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810767410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1810767410
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4037320531
Short name T392
Test name
Test status
Simulation time 60612043 ps
CPU time 1.09 seconds
Started Jul 09 04:37:51 PM PDT 24
Finished Jul 09 04:37:53 PM PDT 24
Peak memory 196392 kb
Host smart-d2544060-5821-44a1-91bc-7e11b32092f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037320531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4037320531
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1641088276
Short name T478
Test name
Test status
Simulation time 318319928 ps
CPU time 1.03 seconds
Started Jul 09 04:37:51 PM PDT 24
Finished Jul 09 04:37:53 PM PDT 24
Peak memory 196104 kb
Host smart-c9efc6f8-c1e2-4c14-91d1-625273c842c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641088276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1641088276
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.450424342
Short name T93
Test name
Test status
Simulation time 4406151260 ps
CPU time 28.18 seconds
Started Jul 09 04:37:55 PM PDT 24
Finished Jul 09 04:38:24 PM PDT 24
Peak memory 198628 kb
Host smart-2d8fa61f-3ffc-444d-8ae0-263a8a0b3a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450424342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.450424342
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3118023922
Short name T32
Test name
Test status
Simulation time 11866813 ps
CPU time 0.55 seconds
Started Jul 09 04:39:23 PM PDT 24
Finished Jul 09 04:39:25 PM PDT 24
Peak memory 195212 kb
Host smart-4a303237-1a9b-4cd6-9c64-06550df03d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118023922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3118023922
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1448608111
Short name T193
Test name
Test status
Simulation time 31701372 ps
CPU time 0.76 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 196568 kb
Host smart-691c5922-7db9-44eb-be4b-956ae0a877a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448608111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1448608111
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.4151546569
Short name T393
Test name
Test status
Simulation time 408097937 ps
CPU time 5.71 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 04:39:31 PM PDT 24
Peak memory 198500 kb
Host smart-f604d604-faea-4437-b134-4c505581d714
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151546569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.4151546569
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.980224556
Short name T582
Test name
Test status
Simulation time 267833701 ps
CPU time 0.92 seconds
Started Jul 09 04:39:25 PM PDT 24
Finished Jul 09 04:39:27 PM PDT 24
Peak memory 197660 kb
Host smart-105e284e-eba4-4ca5-8f9d-733b286248f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980224556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.980224556
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2271275946
Short name T127
Test name
Test status
Simulation time 22570429 ps
CPU time 0.79 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:23 PM PDT 24
Peak memory 195876 kb
Host smart-2feffe4c-f0df-4c01-8236-de6f74cc9d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271275946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2271275946
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3173248682
Short name T521
Test name
Test status
Simulation time 153926424 ps
CPU time 3.12 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:23 PM PDT 24
Peak memory 196836 kb
Host smart-461563e7-08d2-427e-be32-0f8ee4d47a88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173248682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3173248682
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.93237689
Short name T533
Test name
Test status
Simulation time 176231463 ps
CPU time 1.24 seconds
Started Jul 09 04:39:19 PM PDT 24
Finished Jul 09 04:39:21 PM PDT 24
Peak memory 197276 kb
Host smart-3940effa-bdde-405e-9b15-ba8c69e8a01c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93237689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.93237689
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1878742986
Short name T163
Test name
Test status
Simulation time 26700995 ps
CPU time 0.74 seconds
Started Jul 09 04:39:18 PM PDT 24
Finished Jul 09 04:39:20 PM PDT 24
Peak memory 196052 kb
Host smart-e2e9e66c-3575-495c-b4fe-95fecda69943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878742986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1878742986
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.386324154
Short name T354
Test name
Test status
Simulation time 148702412 ps
CPU time 0.91 seconds
Started Jul 09 04:39:21 PM PDT 24
Finished Jul 09 04:39:22 PM PDT 24
Peak memory 196500 kb
Host smart-651693f3-de39-48b5-a721-07aa94b78be9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386324154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.386324154
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3807648288
Short name T2
Test name
Test status
Simulation time 512932811 ps
CPU time 5.85 seconds
Started Jul 09 04:39:23 PM PDT 24
Finished Jul 09 04:39:30 PM PDT 24
Peak memory 198580 kb
Host smart-7aafaf35-67bd-4de3-82ef-e67cc76bb95c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807648288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3807648288
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3769790783
Short name T460
Test name
Test status
Simulation time 32177266 ps
CPU time 0.97 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:28 PM PDT 24
Peak memory 196984 kb
Host smart-60183bc8-0ec1-4944-8fec-588de98045af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769790783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3769790783
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2242710164
Short name T244
Test name
Test status
Simulation time 115656878 ps
CPU time 1.08 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:23 PM PDT 24
Peak memory 196936 kb
Host smart-a1f1f0f6-c12f-4bdd-9c9f-88667c420d2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242710164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2242710164
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.258490957
Short name T689
Test name
Test status
Simulation time 9929326467 ps
CPU time 35.21 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 04:40:00 PM PDT 24
Peak memory 198664 kb
Host smart-e0b7b596-5f34-4c5b-a776-fcbc1a96939b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258490957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.258490957
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.125334994
Short name T52
Test name
Test status
Simulation time 58618119548 ps
CPU time 1608.58 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 05:06:14 PM PDT 24
Peak memory 198772 kb
Host smart-d8c73ded-5e2e-4d72-9690-15209f1637db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=125334994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.125334994
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.112180078
Short name T207
Test name
Test status
Simulation time 14763940 ps
CPU time 0.56 seconds
Started Jul 09 04:39:23 PM PDT 24
Finished Jul 09 04:39:25 PM PDT 24
Peak memory 194560 kb
Host smart-8e6f8348-c4e7-4db1-8318-8b9c9b8b1207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112180078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.112180078
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3275930218
Short name T202
Test name
Test status
Simulation time 28789337 ps
CPU time 0.75 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:30 PM PDT 24
Peak memory 196424 kb
Host smart-ae60d32a-098f-40b3-ac9a-496dbbbeb650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275930218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3275930218
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.203325142
Short name T650
Test name
Test status
Simulation time 514559902 ps
CPU time 26.69 seconds
Started Jul 09 04:39:23 PM PDT 24
Finished Jul 09 04:39:51 PM PDT 24
Peak memory 197516 kb
Host smart-9c928e6e-0fcd-450b-b554-0a2c0a3331e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203325142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.203325142
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3627616636
Short name T577
Test name
Test status
Simulation time 80294396 ps
CPU time 0.87 seconds
Started Jul 09 04:39:31 PM PDT 24
Finished Jul 09 04:39:33 PM PDT 24
Peak memory 197704 kb
Host smart-d3c570ca-d349-481d-a6ce-f177e3791cab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627616636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3627616636
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.897895619
Short name T134
Test name
Test status
Simulation time 31546321 ps
CPU time 0.76 seconds
Started Jul 09 04:39:29 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 194864 kb
Host smart-4de99c39-7962-4ca3-8fd0-c4791011fae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897895619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.897895619
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3508814229
Short name T291
Test name
Test status
Simulation time 186165621 ps
CPU time 3.55 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 198540 kb
Host smart-66887b0f-2837-49cd-8617-93633286ee7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508814229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3508814229
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2325640774
Short name T265
Test name
Test status
Simulation time 98318082 ps
CPU time 3.06 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 04:39:28 PM PDT 24
Peak memory 197628 kb
Host smart-18024524-ce80-41d0-b454-20c27e60ec9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325640774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2325640774
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4236028849
Short name T649
Test name
Test status
Simulation time 135234167 ps
CPU time 0.87 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:31 PM PDT 24
Peak memory 197148 kb
Host smart-13796fcb-65ff-47f9-a0fd-62c399a3c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236028849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4236028849
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2876842493
Short name T635
Test name
Test status
Simulation time 66916460 ps
CPU time 1.2 seconds
Started Jul 09 04:39:25 PM PDT 24
Finished Jul 09 04:39:27 PM PDT 24
Peak memory 197712 kb
Host smart-c2ed2d01-354a-46bb-a724-2ec657254f6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876842493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2876842493
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2355356717
Short name T1
Test name
Test status
Simulation time 8043544489 ps
CPU time 6.56 seconds
Started Jul 09 04:39:25 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 198552 kb
Host smart-2fd716e7-bfd7-4300-b8a9-f847cad92dca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355356717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2355356717
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2745297426
Short name T351
Test name
Test status
Simulation time 77283466 ps
CPU time 1.01 seconds
Started Jul 09 04:39:25 PM PDT 24
Finished Jul 09 04:39:27 PM PDT 24
Peak memory 196372 kb
Host smart-01b30f22-b579-46fc-9cbf-715b967f31e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745297426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2745297426
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1588403596
Short name T300
Test name
Test status
Simulation time 263600014 ps
CPU time 1.11 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 196968 kb
Host smart-26464945-8017-44cd-b103-9b569ee08daf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588403596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1588403596
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.4109815557
Short name T59
Test name
Test status
Simulation time 10143848625 ps
CPU time 71.27 seconds
Started Jul 09 04:39:30 PM PDT 24
Finished Jul 09 04:40:43 PM PDT 24
Peak memory 198668 kb
Host smart-24e39016-a945-43ec-aee3-1ef823b04646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109815557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.4109815557
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.863999495
Short name T14
Test name
Test status
Simulation time 14754530 ps
CPU time 0.59 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:30 PM PDT 24
Peak memory 194712 kb
Host smart-c58d6e28-885a-4dd9-881a-831b7ea4b61f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863999495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.863999495
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3489670560
Short name T692
Test name
Test status
Simulation time 146125191 ps
CPU time 0.96 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:31 PM PDT 24
Peak memory 197012 kb
Host smart-cbf68aca-44e3-478e-95b2-516fdea5b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489670560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3489670560
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1138679545
Short name T150
Test name
Test status
Simulation time 569482774 ps
CPU time 7.12 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:35 PM PDT 24
Peak memory 197452 kb
Host smart-ff2c015e-46ee-4b72-bd85-50997231f3c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138679545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1138679545
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1097907581
Short name T19
Test name
Test status
Simulation time 228277253 ps
CPU time 0.75 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:30 PM PDT 24
Peak memory 196340 kb
Host smart-22bbce95-67db-4a79-b684-b1183c93410f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097907581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1097907581
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.988849729
Short name T376
Test name
Test status
Simulation time 36839145 ps
CPU time 1.02 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:30 PM PDT 24
Peak memory 197048 kb
Host smart-1b22426e-bf7a-4da4-b55a-109a71f810de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988849729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.988849729
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2396917274
Short name T550
Test name
Test status
Simulation time 174396740 ps
CPU time 3.51 seconds
Started Jul 09 04:39:29 PM PDT 24
Finished Jul 09 04:39:35 PM PDT 24
Peak memory 198640 kb
Host smart-8f589c4d-5eee-4044-9079-6509b822d566
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396917274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2396917274
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2050149658
Short name T335
Test name
Test status
Simulation time 96020152 ps
CPU time 2.74 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:33 PM PDT 24
Peak memory 197484 kb
Host smart-09b67b5e-155e-47ea-a31e-e062a29a04bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050149658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2050149658
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.533234277
Short name T125
Test name
Test status
Simulation time 122363804 ps
CPU time 1.26 seconds
Started Jul 09 04:39:22 PM PDT 24
Finished Jul 09 04:39:25 PM PDT 24
Peak memory 196400 kb
Host smart-39f7365f-05b3-4173-820a-949046bdb24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533234277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.533234277
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.325529492
Short name T44
Test name
Test status
Simulation time 251163468 ps
CPU time 0.89 seconds
Started Jul 09 04:39:25 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 196556 kb
Host smart-cbea1a8f-b03b-49ce-a7a7-f7a62f408341
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325529492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.325529492
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.283463632
Short name T395
Test name
Test status
Simulation time 118229038 ps
CPU time 1.18 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:29 PM PDT 24
Peak memory 198532 kb
Host smart-3788fbc4-195c-4113-9340-c1ece01e310e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283463632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.283463632
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.804979437
Short name T208
Test name
Test status
Simulation time 34507404 ps
CPU time 0.96 seconds
Started Jul 09 04:39:24 PM PDT 24
Finished Jul 09 04:39:26 PM PDT 24
Peak memory 196504 kb
Host smart-bd09288f-d3ed-44ef-83c6-e57f69246134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804979437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.804979437
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2181829908
Short name T94
Test name
Test status
Simulation time 258949878 ps
CPU time 0.98 seconds
Started Jul 09 04:39:30 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 196124 kb
Host smart-861a2f22-215d-48bc-8522-72daee1ca710
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181829908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2181829908
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3482726046
Short name T9
Test name
Test status
Simulation time 13617673609 ps
CPU time 153.49 seconds
Started Jul 09 04:39:30 PM PDT 24
Finished Jul 09 04:42:06 PM PDT 24
Peak memory 198628 kb
Host smart-52659d46-ed15-4e36-90f4-980e1a4efdea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482726046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3482726046
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1328165528
Short name T205
Test name
Test status
Simulation time 49305876 ps
CPU time 0.59 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:30 PM PDT 24
Peak memory 195432 kb
Host smart-c9799ca9-e9ca-41c8-90b7-78967d292dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328165528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1328165528
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1807903266
Short name T359
Test name
Test status
Simulation time 68920803 ps
CPU time 0.78 seconds
Started Jul 09 04:39:29 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 195740 kb
Host smart-e94b77b3-92db-40fa-8598-ab8a53fafb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807903266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1807903266
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2267801971
Short name T446
Test name
Test status
Simulation time 423318488 ps
CPU time 10.98 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:40 PM PDT 24
Peak memory 197356 kb
Host smart-60718c22-eeae-4aa2-81a8-3960cf7e3e80
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267801971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2267801971
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.896824118
Short name T606
Test name
Test status
Simulation time 39968317 ps
CPU time 0.72 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 195204 kb
Host smart-ed38a9d2-3af4-4b80-b048-dd3a2b098bc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896824118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.896824118
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2923286823
Short name T172
Test name
Test status
Simulation time 92225269 ps
CPU time 1.5 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:29 PM PDT 24
Peak memory 197508 kb
Host smart-b1c73c3a-60a4-4ba9-acf5-35864d8f15f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923286823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2923286823
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2955167338
Short name T348
Test name
Test status
Simulation time 53252805 ps
CPU time 2.08 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:31 PM PDT 24
Peak memory 198604 kb
Host smart-8035073c-270f-489f-ad86-938e89c33378
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955167338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2955167338
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3831300539
Short name T515
Test name
Test status
Simulation time 159005790 ps
CPU time 3.02 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:33 PM PDT 24
Peak memory 196332 kb
Host smart-340c08a5-2e89-43a8-bab1-c6068dc79c19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831300539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3831300539
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.572058870
Short name T108
Test name
Test status
Simulation time 103130508 ps
CPU time 0.71 seconds
Started Jul 09 04:39:27 PM PDT 24
Finished Jul 09 04:39:28 PM PDT 24
Peak memory 196024 kb
Host smart-29a4be5c-3699-493b-b186-9a917fcab287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572058870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.572058870
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2991513005
Short name T529
Test name
Test status
Simulation time 69566853 ps
CPU time 0.96 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:30 PM PDT 24
Peak memory 196564 kb
Host smart-62f0b0cf-7099-43fe-815d-80f2c384b4a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991513005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2991513005
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3875689049
Short name T470
Test name
Test status
Simulation time 75384420 ps
CPU time 3.24 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 198524 kb
Host smart-c8df1560-18fd-4afc-8a00-74e1b28647cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875689049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3875689049
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2900884035
Short name T118
Test name
Test status
Simulation time 22198432 ps
CPU time 0.84 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:39:31 PM PDT 24
Peak memory 195936 kb
Host smart-d875b411-b484-4ad3-aff0-f80de3e785d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900884035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2900884035
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2317513315
Short name T510
Test name
Test status
Simulation time 239914308 ps
CPU time 1.16 seconds
Started Jul 09 04:39:29 PM PDT 24
Finished Jul 09 04:39:33 PM PDT 24
Peak memory 196932 kb
Host smart-37d9262e-b5c5-470d-87b8-3d4120d0edbc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317513315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2317513315
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1215269694
Short name T642
Test name
Test status
Simulation time 7143947444 ps
CPU time 82.34 seconds
Started Jul 09 04:39:28 PM PDT 24
Finished Jul 09 04:40:53 PM PDT 24
Peak memory 198688 kb
Host smart-068d9ad5-9c9a-4fa4-ba95-812c9e661974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215269694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1215269694
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1668886004
Short name T264
Test name
Test status
Simulation time 29748787 ps
CPU time 0.61 seconds
Started Jul 09 04:39:31 PM PDT 24
Finished Jul 09 04:39:33 PM PDT 24
Peak memory 194604 kb
Host smart-fa4d2ba9-b575-43b4-b533-307cd0c39d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668886004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1668886004
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2975019336
Short name T274
Test name
Test status
Simulation time 90848967 ps
CPU time 0.88 seconds
Started Jul 09 04:39:31 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 196724 kb
Host smart-dab575c7-67a7-4dda-a9bc-091000936a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975019336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2975019336
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.827159466
Short name T15
Test name
Test status
Simulation time 1903569271 ps
CPU time 13.64 seconds
Started Jul 09 04:39:32 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 196076 kb
Host smart-a9aada15-6891-4c5e-a2c9-ce9185c29fe0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827159466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.827159466
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.795584039
Short name T617
Test name
Test status
Simulation time 247558874 ps
CPU time 0.81 seconds
Started Jul 09 04:39:32 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 196496 kb
Host smart-52d4e809-cd5d-4ea3-941b-81f8a40fe6b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795584039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.795584039
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.630291718
Short name T356
Test name
Test status
Simulation time 258215630 ps
CPU time 1.03 seconds
Started Jul 09 04:39:29 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 196520 kb
Host smart-c88b85e9-87e7-4f1d-9b8e-df15d071ef62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630291718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.630291718
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1385335723
Short name T625
Test name
Test status
Simulation time 161948134 ps
CPU time 1.78 seconds
Started Jul 09 04:39:33 PM PDT 24
Finished Jul 09 04:39:36 PM PDT 24
Peak memory 198648 kb
Host smart-63d73ad5-b510-4c77-b155-d171a0a7b98f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385335723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1385335723
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3708632526
Short name T269
Test name
Test status
Simulation time 348794605 ps
CPU time 1.92 seconds
Started Jul 09 04:39:30 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 197296 kb
Host smart-862daaff-c97a-47cd-96fa-86bfd8a2e157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708632526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3708632526
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3700488810
Short name T253
Test name
Test status
Simulation time 65057832 ps
CPU time 1.27 seconds
Started Jul 09 04:39:30 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 197448 kb
Host smart-5ef5b317-8457-4b60-85ab-fc0a364866c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700488810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3700488810
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1230208631
Short name T90
Test name
Test status
Simulation time 466643063 ps
CPU time 1.31 seconds
Started Jul 09 04:39:31 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 198604 kb
Host smart-ff78449c-3311-4d84-9ef5-6a6f5b4b2239
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230208631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1230208631
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.532677138
Short name T260
Test name
Test status
Simulation time 88763408 ps
CPU time 4.07 seconds
Started Jul 09 04:39:34 PM PDT 24
Finished Jul 09 04:39:39 PM PDT 24
Peak memory 198464 kb
Host smart-26a9758a-72eb-4e1b-962d-3c18267edcdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532677138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.532677138
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.227652717
Short name T426
Test name
Test status
Simulation time 217996618 ps
CPU time 1.27 seconds
Started Jul 09 04:39:29 PM PDT 24
Finished Jul 09 04:39:33 PM PDT 24
Peak memory 196344 kb
Host smart-80af292b-7807-44df-a894-7d539ff3c7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227652717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.227652717
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.772897482
Short name T113
Test name
Test status
Simulation time 85280763 ps
CPU time 1.33 seconds
Started Jul 09 04:39:26 PM PDT 24
Finished Jul 09 04:39:28 PM PDT 24
Peak memory 198576 kb
Host smart-860bc09a-b5aa-47d4-a214-7fe870186ac0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772897482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.772897482
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1099960612
Short name T190
Test name
Test status
Simulation time 46097639358 ps
CPU time 115.95 seconds
Started Jul 09 04:39:33 PM PDT 24
Finished Jul 09 04:41:31 PM PDT 24
Peak memory 198608 kb
Host smart-dc13b407-5eed-4739-adad-ce1638230561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099960612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1099960612
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2422550074
Short name T268
Test name
Test status
Simulation time 16763672 ps
CPU time 0.58 seconds
Started Jul 09 04:39:37 PM PDT 24
Finished Jul 09 04:39:38 PM PDT 24
Peak memory 195320 kb
Host smart-12a3c4f4-cf3f-4abb-bd13-2a9d45e3605e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422550074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2422550074
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2269544092
Short name T541
Test name
Test status
Simulation time 78054388 ps
CPU time 0.71 seconds
Started Jul 09 04:39:33 PM PDT 24
Finished Jul 09 04:39:35 PM PDT 24
Peak memory 196368 kb
Host smart-18827c5f-8d66-47f1-868f-c8017bc3eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269544092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2269544092
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.314728606
Short name T581
Test name
Test status
Simulation time 160645053 ps
CPU time 5.33 seconds
Started Jul 09 04:39:40 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 196036 kb
Host smart-a2ad7c5e-01c8-47ea-bc1e-dcb56cc51171
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314728606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.314728606
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.529129380
Short name T636
Test name
Test status
Simulation time 21345166 ps
CPU time 0.58 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 195424 kb
Host smart-81067bf2-5bce-4bd8-a533-4c3e8cc2bd25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529129380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.529129380
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.286531072
Short name T231
Test name
Test status
Simulation time 89629928 ps
CPU time 1.29 seconds
Started Jul 09 04:39:34 PM PDT 24
Finished Jul 09 04:39:36 PM PDT 24
Peak memory 197324 kb
Host smart-03cfa73c-2669-4455-a47f-85f26cca0cab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286531072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.286531072
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1862576466
Short name T428
Test name
Test status
Simulation time 32763135 ps
CPU time 1.37 seconds
Started Jul 09 04:39:31 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 196828 kb
Host smart-e98e12a2-8581-44bd-a04d-1cd2367da9f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862576466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1862576466
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3178914043
Short name T390
Test name
Test status
Simulation time 103203338 ps
CPU time 2.65 seconds
Started Jul 09 04:39:32 PM PDT 24
Finished Jul 09 04:39:37 PM PDT 24
Peak memory 197920 kb
Host smart-0a55d8fd-be70-4684-abc2-3fbb9378ef4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178914043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3178914043
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1369244811
Short name T491
Test name
Test status
Simulation time 22232419 ps
CPU time 0.88 seconds
Started Jul 09 04:39:35 PM PDT 24
Finished Jul 09 04:39:36 PM PDT 24
Peak memory 196564 kb
Host smart-58332c50-d9b8-4dc6-af6c-4dd9fcd296d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369244811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1369244811
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3435411348
Short name T712
Test name
Test status
Simulation time 204803390 ps
CPU time 1.21 seconds
Started Jul 09 04:39:33 PM PDT 24
Finished Jul 09 04:39:35 PM PDT 24
Peak memory 197160 kb
Host smart-b8cfdc45-45bc-4c02-829b-fcd020124df6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435411348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3435411348
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2138532744
Short name T223
Test name
Test status
Simulation time 509403430 ps
CPU time 5.85 seconds
Started Jul 09 04:39:32 PM PDT 24
Finished Jul 09 04:39:39 PM PDT 24
Peak memory 198532 kb
Host smart-6ac7d2d4-86e3-4641-887f-bc947407c00a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138532744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2138532744
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1292334463
Short name T556
Test name
Test status
Simulation time 115335548 ps
CPU time 0.99 seconds
Started Jul 09 04:39:40 PM PDT 24
Finished Jul 09 04:39:42 PM PDT 24
Peak memory 196056 kb
Host smart-898177b5-28c4-43f4-8cc0-698d4b7bc74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292334463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1292334463
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3387143243
Short name T272
Test name
Test status
Simulation time 83163493 ps
CPU time 0.8 seconds
Started Jul 09 04:39:31 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 195800 kb
Host smart-d0884572-64f2-494e-a045-92ec2b832285
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387143243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3387143243
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1528406913
Short name T630
Test name
Test status
Simulation time 13800842581 ps
CPU time 189.17 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:42:56 PM PDT 24
Peak memory 198684 kb
Host smart-bad88b04-31c2-4b91-99ae-725be48c947c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528406913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1528406913
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1132853706
Short name T322
Test name
Test status
Simulation time 178077137 ps
CPU time 0.63 seconds
Started Jul 09 04:39:36 PM PDT 24
Finished Jul 09 04:39:37 PM PDT 24
Peak memory 195412 kb
Host smart-f62e5aac-6b2a-4223-bed2-59e8e4642459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132853706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1132853706
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.322998324
Short name T47
Test name
Test status
Simulation time 34830998 ps
CPU time 0.74 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:44 PM PDT 24
Peak memory 196404 kb
Host smart-f1c414fd-ad30-45d6-83b3-de6d6800d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322998324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.322998324
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1405938723
Short name T174
Test name
Test status
Simulation time 383780208 ps
CPU time 12.35 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:56 PM PDT 24
Peak memory 197492 kb
Host smart-6247fc43-10dc-4d49-92fe-764537115e49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405938723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1405938723
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.937886786
Short name T680
Test name
Test status
Simulation time 469629953 ps
CPU time 1.05 seconds
Started Jul 09 04:39:38 PM PDT 24
Finished Jul 09 04:39:40 PM PDT 24
Peak memory 197224 kb
Host smart-6f870916-f16c-41e1-b0fc-891f034e8547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937886786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.937886786
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2922808677
Short name T570
Test name
Test status
Simulation time 194954067 ps
CPU time 0.89 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 195952 kb
Host smart-069e2148-87d1-4180-9334-7d65770bee75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922808677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2922808677
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2295533285
Short name T628
Test name
Test status
Simulation time 120623070 ps
CPU time 1.38 seconds
Started Jul 09 04:39:40 PM PDT 24
Finished Jul 09 04:39:41 PM PDT 24
Peak memory 197160 kb
Host smart-5ce6b2a5-c83c-4016-8e99-8923e5a44b95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295533285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2295533285
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.327113269
Short name T656
Test name
Test status
Simulation time 131421333 ps
CPU time 1.16 seconds
Started Jul 09 04:39:39 PM PDT 24
Finished Jul 09 04:39:41 PM PDT 24
Peak memory 197132 kb
Host smart-bedf696e-3e1b-4730-a998-c4d4e91ae423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327113269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
327113269
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.81174953
Short name T571
Test name
Test status
Simulation time 31031642 ps
CPU time 0.84 seconds
Started Jul 09 04:39:45 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 196980 kb
Host smart-08e63135-172c-42c5-84a3-852b690886d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81174953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.81174953
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2354957402
Short name T718
Test name
Test status
Simulation time 115152961 ps
CPU time 1.34 seconds
Started Jul 09 04:39:37 PM PDT 24
Finished Jul 09 04:39:39 PM PDT 24
Peak memory 197684 kb
Host smart-0ff3d27e-0045-43c9-a39c-737def1c8661
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354957402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2354957402
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1345313358
Short name T455
Test name
Test status
Simulation time 235633238 ps
CPU time 4.06 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 198500 kb
Host smart-404d1bbd-4ef8-49b3-b520-0786d7e05781
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345313358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1345313358
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1821800113
Short name T490
Test name
Test status
Simulation time 326507486 ps
CPU time 0.99 seconds
Started Jul 09 04:39:40 PM PDT 24
Finished Jul 09 04:39:41 PM PDT 24
Peak memory 196956 kb
Host smart-182d5cb2-d8d4-4fa0-915a-1efbf4183a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821800113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1821800113
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3945671831
Short name T182
Test name
Test status
Simulation time 219293858 ps
CPU time 1 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:44 PM PDT 24
Peak memory 196420 kb
Host smart-7895bd83-4046-4dc0-a443-a906a568bc82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945671831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3945671831
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4204370435
Short name T3
Test name
Test status
Simulation time 16371979078 ps
CPU time 166.59 seconds
Started Jul 09 04:39:39 PM PDT 24
Finished Jul 09 04:42:26 PM PDT 24
Peak memory 198528 kb
Host smart-f956b836-1ae4-4b79-b6b8-f3e3abb91ac2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204370435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4204370435
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.4043498668
Short name T509
Test name
Test status
Simulation time 88692347 ps
CPU time 0.57 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:44 PM PDT 24
Peak memory 194752 kb
Host smart-bdf294fe-4582-4a16-9928-d8e20fc4ce55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043498668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4043498668
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4218761510
Short name T669
Test name
Test status
Simulation time 104067153 ps
CPU time 0.72 seconds
Started Jul 09 04:39:37 PM PDT 24
Finished Jul 09 04:39:39 PM PDT 24
Peak memory 196392 kb
Host smart-b1abf834-6d82-4307-8a39-ff0b5aa98f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218761510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.4218761510
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2880407609
Short name T702
Test name
Test status
Simulation time 595875629 ps
CPU time 19.66 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:40:03 PM PDT 24
Peak memory 197448 kb
Host smart-f36c26fd-c9d5-442c-9811-2ea04fa1070b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880407609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2880407609
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3930375861
Short name T342
Test name
Test status
Simulation time 81221544 ps
CPU time 1.01 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 197156 kb
Host smart-d7f50c82-270d-4e0e-b373-92f50600a4f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930375861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3930375861
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3271196020
Short name T232
Test name
Test status
Simulation time 67102466 ps
CPU time 1.16 seconds
Started Jul 09 04:39:45 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 196440 kb
Host smart-24dead38-0c71-4df1-8f23-af0af85829a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271196020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3271196020
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1967634352
Short name T185
Test name
Test status
Simulation time 287069581 ps
CPU time 2.78 seconds
Started Jul 09 04:39:40 PM PDT 24
Finished Jul 09 04:39:44 PM PDT 24
Peak memory 198556 kb
Host smart-673ee044-131a-4617-bad6-3309d87e3b03
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967634352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1967634352
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1609897121
Short name T697
Test name
Test status
Simulation time 595163616 ps
CPU time 3.26 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:49 PM PDT 24
Peak memory 196384 kb
Host smart-9836dc6b-bc9f-4aa9-abe6-15983301f04f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609897121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1609897121
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.4141204843
Short name T353
Test name
Test status
Simulation time 292532711 ps
CPU time 1.41 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 198664 kb
Host smart-6e919212-1a26-430c-a00e-c682fbb60328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141204843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.4141204843
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.4106326165
Short name T618
Test name
Test status
Simulation time 65475919 ps
CPU time 0.85 seconds
Started Jul 09 04:39:37 PM PDT 24
Finished Jul 09 04:39:38 PM PDT 24
Peak memory 196344 kb
Host smart-35ca61b4-fbc6-4430-b02d-cc04f4e98c78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106326165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.4106326165
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3029983979
Short name T160
Test name
Test status
Simulation time 188728053 ps
CPU time 4.65 seconds
Started Jul 09 04:39:37 PM PDT 24
Finished Jul 09 04:39:42 PM PDT 24
Peak memory 198684 kb
Host smart-21e3555a-73be-4604-a1f0-455d6f6cf9b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029983979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3029983979
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.658818447
Short name T105
Test name
Test status
Simulation time 49594367 ps
CPU time 1.06 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 196320 kb
Host smart-8c54ae82-663e-48ca-ace7-226212bd3b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658818447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.658818447
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.820999832
Short name T278
Test name
Test status
Simulation time 50049323 ps
CPU time 1.09 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 196760 kb
Host smart-5a9c2e0b-7f56-4cc6-87b3-17d329e4f206
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820999832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.820999832
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.4187638967
Short name T374
Test name
Test status
Simulation time 5221530005 ps
CPU time 67.49 seconds
Started Jul 09 04:39:37 PM PDT 24
Finished Jul 09 04:40:45 PM PDT 24
Peak memory 198764 kb
Host smart-c00977d7-0726-482c-b357-a18f3382c69e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187638967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.4187638967
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3240407753
Short name T681
Test name
Test status
Simulation time 233615195590 ps
CPU time 553.58 seconds
Started Jul 09 04:39:52 PM PDT 24
Finished Jul 09 04:49:06 PM PDT 24
Peak memory 198628 kb
Host smart-d0d55ab3-fc91-4e0e-af23-94269aa42ae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3240407753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3240407753
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1137273197
Short name T133
Test name
Test status
Simulation time 52997050 ps
CPU time 0.57 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 194580 kb
Host smart-77df3e5d-77f6-4be1-a9bc-37a1c2657ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137273197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1137273197
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.4291744171
Short name T670
Test name
Test status
Simulation time 25867195 ps
CPU time 0.7 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 195336 kb
Host smart-a6efe45b-beb8-4e27-9b39-107e7392d532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291744171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.4291744171
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1005994197
Short name T334
Test name
Test status
Simulation time 2283605443 ps
CPU time 19.65 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:40:01 PM PDT 24
Peak memory 197740 kb
Host smart-dbea8568-2875-4148-b514-fb9550c84a68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005994197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1005994197
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1799975809
Short name T170
Test name
Test status
Simulation time 37277203 ps
CPU time 0.83 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 197192 kb
Host smart-31870f6f-c422-48f7-a6a0-8650bae4dcf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799975809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1799975809
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3922276919
Short name T471
Test name
Test status
Simulation time 73013466 ps
CPU time 1.06 seconds
Started Jul 09 04:39:49 PM PDT 24
Finished Jul 09 04:39:51 PM PDT 24
Peak memory 196692 kb
Host smart-155d07c5-929b-4106-91aa-02bc7ce29df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922276919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3922276919
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2323111251
Short name T481
Test name
Test status
Simulation time 63762425 ps
CPU time 1.28 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 196956 kb
Host smart-d2ecc84c-dbe6-42ae-b741-5f5c32a4ec92
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323111251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2323111251
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1328952557
Short name T597
Test name
Test status
Simulation time 220967478 ps
CPU time 1.92 seconds
Started Jul 09 04:39:46 PM PDT 24
Finished Jul 09 04:39:50 PM PDT 24
Peak memory 197208 kb
Host smart-14c91cb6-4675-431f-b0a3-c254090c6614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328952557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1328952557
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.344368809
Short name T363
Test name
Test status
Simulation time 98897348 ps
CPU time 1.15 seconds
Started Jul 09 04:39:44 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 196360 kb
Host smart-289618a0-b3e5-4ed3-bd0f-f0245a48a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344368809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.344368809
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.116720245
Short name T132
Test name
Test status
Simulation time 46481859 ps
CPU time 0.74 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 195940 kb
Host smart-f56a83d5-966c-45e5-b810-c4d720220044
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116720245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.116720245
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1255838225
Short name T164
Test name
Test status
Simulation time 104826920 ps
CPU time 4.85 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 198492 kb
Host smart-c1e88ec8-1a0f-4fb2-893b-22e499d3ae7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255838225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1255838225
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3249470599
Short name T179
Test name
Test status
Simulation time 49353529 ps
CPU time 0.7 seconds
Started Jul 09 04:39:39 PM PDT 24
Finished Jul 09 04:39:40 PM PDT 24
Peak memory 195704 kb
Host smart-7f17658d-c46d-4712-a2a5-4fb82f66380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249470599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3249470599
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3964171908
Short name T383
Test name
Test status
Simulation time 133891407 ps
CPU time 1.38 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 196084 kb
Host smart-31434c19-4035-414d-aedb-617542c67d7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964171908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3964171908
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3682805535
Short name T219
Test name
Test status
Simulation time 50194358480 ps
CPU time 203.44 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:43:08 PM PDT 24
Peak memory 198740 kb
Host smart-cfdc9590-ce34-4d37-bb88-7738ec88b388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682805535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3682805535
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3556581700
Short name T445
Test name
Test status
Simulation time 149336136938 ps
CPU time 233.62 seconds
Started Jul 09 04:39:39 PM PDT 24
Finished Jul 09 04:43:33 PM PDT 24
Peak memory 206972 kb
Host smart-0aa4052e-6b7a-4dab-8fb7-20925f3eef5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3556581700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3556581700
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3052925161
Short name T116
Test name
Test status
Simulation time 103321568 ps
CPU time 0.6 seconds
Started Jul 09 04:39:45 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 194512 kb
Host smart-f23790e6-9b72-4779-8701-526fe5c01954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052925161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3052925161
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.4187434979
Short name T254
Test name
Test status
Simulation time 40941481 ps
CPU time 0.95 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:44 PM PDT 24
Peak memory 196492 kb
Host smart-bbd9a935-8161-423a-91d1-e46622e78f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187434979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.4187434979
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2671642831
Short name T385
Test name
Test status
Simulation time 888658207 ps
CPU time 10.6 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:55 PM PDT 24
Peak memory 197400 kb
Host smart-03598f87-644f-4ad2-b0de-df0157dab3f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671642831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2671642831
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3272994958
Short name T178
Test name
Test status
Simulation time 33458876 ps
CPU time 0.67 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:42 PM PDT 24
Peak memory 195172 kb
Host smart-b67f12b9-b3b3-4abc-bdc0-dfc420106de5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272994958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3272994958
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3775965928
Short name T299
Test name
Test status
Simulation time 104667946 ps
CPU time 0.98 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 197276 kb
Host smart-51ce5b24-fced-45d2-b237-4ef697ae9649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775965928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3775965928
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1348579339
Short name T513
Test name
Test status
Simulation time 54067349 ps
CPU time 1.64 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 196692 kb
Host smart-0d1bc9cb-2386-4097-b50d-c9ef9c9f4552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348579339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1348579339
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3983685658
Short name T106
Test name
Test status
Simulation time 79824082 ps
CPU time 0.74 seconds
Started Jul 09 04:39:41 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 195976 kb
Host smart-51690fc0-fdf3-40ed-8144-0be06b525987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983685658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3983685658
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.218244529
Short name T662
Test name
Test status
Simulation time 99963789 ps
CPU time 1.1 seconds
Started Jul 09 04:39:40 PM PDT 24
Finished Jul 09 04:39:41 PM PDT 24
Peak memory 196552 kb
Host smart-e6f8b732-c39a-46ae-95be-e51ab068832b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218244529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.218244529
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2875047722
Short name T677
Test name
Test status
Simulation time 355421650 ps
CPU time 5.31 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:50 PM PDT 24
Peak memory 198464 kb
Host smart-e962298a-7718-4ff3-88fc-c8da5a1aae09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875047722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2875047722
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3161016168
Short name T709
Test name
Test status
Simulation time 58831783 ps
CPU time 1.06 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 196216 kb
Host smart-857b647b-287b-4357-a4e5-1e2e923b22a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161016168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3161016168
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.417608568
Short name T50
Test name
Test status
Simulation time 58803231 ps
CPU time 0.7 seconds
Started Jul 09 04:39:43 PM PDT 24
Finished Jul 09 04:39:46 PM PDT 24
Peak memory 194696 kb
Host smart-7a637689-5d9c-4686-9da5-e5c412c0bb7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417608568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.417608568
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1875823612
Short name T51
Test name
Test status
Simulation time 23257787044 ps
CPU time 142.59 seconds
Started Jul 09 04:39:42 PM PDT 24
Finished Jul 09 04:42:07 PM PDT 24
Peak memory 198768 kb
Host smart-6e74eab5-aa9e-41ed-b149-00afeb14d63f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875823612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1875823612
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2924440588
Short name T297
Test name
Test status
Simulation time 42894575 ps
CPU time 0.58 seconds
Started Jul 09 04:37:55 PM PDT 24
Finished Jul 09 04:37:57 PM PDT 24
Peak memory 194740 kb
Host smart-d2b00409-3eef-4236-b723-6c9a800c63aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924440588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2924440588
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1425333698
Short name T407
Test name
Test status
Simulation time 27826789 ps
CPU time 0.88 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:01 PM PDT 24
Peak memory 195868 kb
Host smart-4cff9237-a4aa-4c3e-943b-55b01229fc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425333698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1425333698
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3696817241
Short name T237
Test name
Test status
Simulation time 650940011 ps
CPU time 16.67 seconds
Started Jul 09 04:37:55 PM PDT 24
Finished Jul 09 04:38:13 PM PDT 24
Peak memory 198540 kb
Host smart-93cf5d4e-2217-49fb-924b-b125655b2b16
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696817241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3696817241
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.450847120
Short name T418
Test name
Test status
Simulation time 43198865 ps
CPU time 0.77 seconds
Started Jul 09 04:37:56 PM PDT 24
Finished Jul 09 04:37:57 PM PDT 24
Peak memory 197108 kb
Host smart-57ed584e-f1fb-427c-ae87-af677bbbb7ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450847120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.450847120
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2854914486
Short name T123
Test name
Test status
Simulation time 149067184 ps
CPU time 1.29 seconds
Started Jul 09 04:37:53 PM PDT 24
Finished Jul 09 04:37:55 PM PDT 24
Peak memory 198612 kb
Host smart-dd649cc0-e518-476a-bdd9-cc15a30aa8f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854914486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2854914486
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.379678252
Short name T271
Test name
Test status
Simulation time 98115149 ps
CPU time 3.35 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 198588 kb
Host smart-101cd7f3-2cdf-404c-a917-e63c7773085b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379678252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.379678252
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.263366828
Short name T495
Test name
Test status
Simulation time 741645273 ps
CPU time 1.97 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 196392 kb
Host smart-ab9b9ed1-ea8c-4a33-a535-081916d922de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263366828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.263366828
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1752158306
Short name T584
Test name
Test status
Simulation time 54890042 ps
CPU time 1.21 seconds
Started Jul 09 04:37:54 PM PDT 24
Finished Jul 09 04:37:56 PM PDT 24
Peak memory 197508 kb
Host smart-1d62fa76-f738-4909-9960-35e22e50de14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752158306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1752158306
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.647138364
Short name T704
Test name
Test status
Simulation time 18592638 ps
CPU time 0.69 seconds
Started Jul 09 04:37:53 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 195456 kb
Host smart-d33f3604-c715-4bd8-a62f-d6019540c062
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647138364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.647138364
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1964487820
Short name T204
Test name
Test status
Simulation time 313967191 ps
CPU time 3.75 seconds
Started Jul 09 04:37:55 PM PDT 24
Finished Jul 09 04:38:00 PM PDT 24
Peak memory 198544 kb
Host smart-2a666240-76f8-4d3c-8d4d-1eb313529e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964487820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1964487820
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.702690571
Short name T275
Test name
Test status
Simulation time 68790830 ps
CPU time 1.2 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 197312 kb
Host smart-486d8492-0785-4e3d-9416-2062e1cf8545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702690571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.702690571
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3529308396
Short name T43
Test name
Test status
Simulation time 463472570 ps
CPU time 1.16 seconds
Started Jul 09 04:37:52 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 197204 kb
Host smart-b96ad642-654f-4f15-af49-0342a6107611
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529308396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3529308396
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3940721864
Short name T256
Test name
Test status
Simulation time 49700369557 ps
CPU time 133.11 seconds
Started Jul 09 04:37:54 PM PDT 24
Finished Jul 09 04:40:08 PM PDT 24
Peak memory 198684 kb
Host smart-153bc694-ef70-436d-a420-50a049768068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940721864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3940721864
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2772943387
Short name T379
Test name
Test status
Simulation time 26228494 ps
CPU time 0.57 seconds
Started Jul 09 04:37:58 PM PDT 24
Finished Jul 09 04:37:59 PM PDT 24
Peak memory 194508 kb
Host smart-466b2b0d-92c4-4ee3-b11b-7347e1500b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772943387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2772943387
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3341907706
Short name T242
Test name
Test status
Simulation time 159079427 ps
CPU time 0.94 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:00 PM PDT 24
Peak memory 196540 kb
Host smart-58830823-5138-43f7-a8d0-9d72e6bb9151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341907706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3341907706
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.108154087
Short name T665
Test name
Test status
Simulation time 1951453965 ps
CPU time 15.29 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:17 PM PDT 24
Peak memory 197620 kb
Host smart-210db1e3-226f-4c63-ae1a-1b75ec196644
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108154087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.108154087
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.714642903
Short name T251
Test name
Test status
Simulation time 222962598 ps
CPU time 0.98 seconds
Started Jul 09 04:37:58 PM PDT 24
Finished Jul 09 04:38:00 PM PDT 24
Peak memory 197124 kb
Host smart-a6a47c44-8b9c-4e04-b309-c6d66b1ef40b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714642903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.714642903
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1140246859
Short name T602
Test name
Test status
Simulation time 198004140 ps
CPU time 1.38 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 197560 kb
Host smart-5de9a343-5ea8-4423-8f4f-14e1180b7cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140246859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1140246859
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2660822841
Short name T304
Test name
Test status
Simulation time 77748689 ps
CPU time 1.66 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 196928 kb
Host smart-10f50e2c-6dac-47ab-8d06-b83389b41fc1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660822841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2660822841
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.125360696
Short name T398
Test name
Test status
Simulation time 260697709 ps
CPU time 1.92 seconds
Started Jul 09 04:37:57 PM PDT 24
Finished Jul 09 04:37:59 PM PDT 24
Peak memory 197432 kb
Host smart-6ae7d00d-950c-4bb2-b350-7bcf2c63ad1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125360696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.125360696
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1984400713
Short name T423
Test name
Test status
Simulation time 35586620 ps
CPU time 1.24 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 197612 kb
Host smart-2adae765-8508-4092-aece-6f188427764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984400713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1984400713
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2049870762
Short name T266
Test name
Test status
Simulation time 135022790 ps
CPU time 1.21 seconds
Started Jul 09 04:37:54 PM PDT 24
Finished Jul 09 04:37:56 PM PDT 24
Peak memory 196600 kb
Host smart-246487ec-6671-4717-8974-20e93461f4a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049870762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2049870762
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1143375765
Short name T307
Test name
Test status
Simulation time 77937102 ps
CPU time 1.73 seconds
Started Jul 09 04:38:01 PM PDT 24
Finished Jul 09 04:38:04 PM PDT 24
Peak memory 198448 kb
Host smart-f0a0bfe3-6b8e-4967-937b-9c35887b1fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143375765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1143375765
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2301180572
Short name T222
Test name
Test status
Simulation time 83045474 ps
CPU time 1.21 seconds
Started Jul 09 04:37:56 PM PDT 24
Finished Jul 09 04:37:58 PM PDT 24
Peak memory 196120 kb
Host smart-5e27847d-67ee-4207-9026-2755f09fccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301180572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2301180572
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1378220984
Short name T391
Test name
Test status
Simulation time 66450949 ps
CPU time 1.16 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 196928 kb
Host smart-c91ae390-0069-4817-a786-f14d62aba32a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378220984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1378220984
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2581850108
Short name T8
Test name
Test status
Simulation time 41243120918 ps
CPU time 118.36 seconds
Started Jul 09 04:37:57 PM PDT 24
Finished Jul 09 04:39:56 PM PDT 24
Peak memory 198612 kb
Host smart-24960346-01c0-465b-9524-31c210781ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581850108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2581850108
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.4030392801
Short name T414
Test name
Test status
Simulation time 587921102290 ps
CPU time 882.73 seconds
Started Jul 09 04:37:58 PM PDT 24
Finished Jul 09 04:52:41 PM PDT 24
Peak memory 206964 kb
Host smart-6516093c-81a0-4222-abeb-307c3d443587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4030392801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.4030392801
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1392157934
Short name T691
Test name
Test status
Simulation time 70997758 ps
CPU time 0.58 seconds
Started Jul 09 04:38:02 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 194764 kb
Host smart-9b5c9309-f206-45a6-9d51-17f9027079a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392157934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1392157934
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3044236407
Short name T124
Test name
Test status
Simulation time 47016638 ps
CPU time 0.66 seconds
Started Jul 09 04:37:57 PM PDT 24
Finished Jul 09 04:37:59 PM PDT 24
Peak memory 194524 kb
Host smart-c2e0592a-a840-4243-9eb3-40e54f9f7067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044236407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3044236407
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3732618244
Short name T295
Test name
Test status
Simulation time 2753085179 ps
CPU time 19.01 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:20 PM PDT 24
Peak memory 197136 kb
Host smart-c89b175e-b420-40aa-8c6c-09ac6941cd39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732618244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3732618244
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3081704626
Short name T245
Test name
Test status
Simulation time 173012593 ps
CPU time 1.04 seconds
Started Jul 09 04:38:01 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 196868 kb
Host smart-e1ec04a1-d729-44e9-a535-c47945e35678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081704626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3081704626
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.450391537
Short name T280
Test name
Test status
Simulation time 24924912 ps
CPU time 0.68 seconds
Started Jul 09 04:37:58 PM PDT 24
Finished Jul 09 04:38:00 PM PDT 24
Peak memory 195092 kb
Host smart-5234d343-b39f-4ed9-b28e-c0183062847d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450391537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.450391537
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.706348882
Short name T228
Test name
Test status
Simulation time 162659987 ps
CPU time 3.24 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:04 PM PDT 24
Peak memory 196876 kb
Host smart-109f0c0f-de97-41a5-a9e7-cee6702c18d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706348882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.706348882
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2683406717
Short name T518
Test name
Test status
Simulation time 623096214 ps
CPU time 1.4 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 196300 kb
Host smart-34ad44b1-29bc-44f0-96d0-76c6972d894a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683406717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2683406717
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3197781251
Short name T329
Test name
Test status
Simulation time 61700351 ps
CPU time 1.11 seconds
Started Jul 09 04:37:58 PM PDT 24
Finished Jul 09 04:37:59 PM PDT 24
Peak memory 196444 kb
Host smart-0020707c-206c-4089-be88-68a75e26ce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197781251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3197781251
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3050473627
Short name T420
Test name
Test status
Simulation time 104909688 ps
CPU time 0.77 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:01 PM PDT 24
Peak memory 195932 kb
Host smart-34f8da28-05cb-4981-ab00-d1b2edd0d7e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050473627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3050473627
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3388488929
Short name T707
Test name
Test status
Simulation time 55632765 ps
CPU time 1.38 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 198508 kb
Host smart-62100d51-262c-4b18-9878-77cc870c81e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388488929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3388488929
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1300326010
Short name T216
Test name
Test status
Simulation time 156110011 ps
CPU time 0.98 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 196252 kb
Host smart-e96f2fdf-1dd1-438b-a696-84083e0589bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300326010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1300326010
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2271037165
Short name T609
Test name
Test status
Simulation time 131382700 ps
CPU time 1.26 seconds
Started Jul 09 04:37:59 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 197464 kb
Host smart-706a7801-eb8d-4531-a716-79ab451a27c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271037165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2271037165
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2608501350
Short name T559
Test name
Test status
Simulation time 7204895835 ps
CPU time 83.93 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:39:25 PM PDT 24
Peak memory 198612 kb
Host smart-fd3a810c-aa76-4d85-8953-1f1eb0efb645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608501350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2608501350
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1825856666
Short name T421
Test name
Test status
Simulation time 29552525 ps
CPU time 0.56 seconds
Started Jul 09 04:38:00 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 195372 kb
Host smart-0d191f3e-449c-4e13-9ec9-15717022046e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825856666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1825856666
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2980432227
Short name T634
Test name
Test status
Simulation time 220997946 ps
CPU time 0.69 seconds
Started Jul 09 04:38:03 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 194772 kb
Host smart-5a507fc8-4738-4b56-8ead-f50703d527e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980432227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2980432227
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3904154728
Short name T664
Test name
Test status
Simulation time 154916094 ps
CPU time 8.02 seconds
Started Jul 09 04:38:02 PM PDT 24
Finished Jul 09 04:38:11 PM PDT 24
Peak memory 198536 kb
Host smart-c657d305-5d31-49c8-b498-4313d194a613
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904154728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3904154728
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.493013696
Short name T474
Test name
Test status
Simulation time 175709552 ps
CPU time 0.95 seconds
Started Jul 09 04:38:09 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 196988 kb
Host smart-29e8dd85-f2d1-4c27-a3d0-b57571ffad0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493013696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.493013696
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1177402544
Short name T477
Test name
Test status
Simulation time 35443158 ps
CPU time 0.76 seconds
Started Jul 09 04:38:04 PM PDT 24
Finished Jul 09 04:38:06 PM PDT 24
Peak memory 196924 kb
Host smart-2fe87e8a-1377-47f0-8a7a-4e3bd45382e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177402544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1177402544
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3656006977
Short name T600
Test name
Test status
Simulation time 46336684 ps
CPU time 1.89 seconds
Started Jul 09 04:38:11 PM PDT 24
Finished Jul 09 04:38:14 PM PDT 24
Peak memory 198432 kb
Host smart-6b23b23d-2cee-44e2-b824-4854ddc55446
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656006977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3656006977
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2360760932
Short name T247
Test name
Test status
Simulation time 89646472 ps
CPU time 0.92 seconds
Started Jul 09 04:38:02 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 196204 kb
Host smart-5333ce51-2dfb-4615-90d9-f1a32317ae4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360760932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2360760932
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2063714205
Short name T457
Test name
Test status
Simulation time 173615844 ps
CPU time 1.01 seconds
Started Jul 09 04:38:03 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 196740 kb
Host smart-097eaf44-4ccd-4470-af0f-c333a42e82c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063714205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2063714205
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3656250066
Short name T263
Test name
Test status
Simulation time 233704945 ps
CPU time 1.21 seconds
Started Jul 09 04:38:06 PM PDT 24
Finished Jul 09 04:38:08 PM PDT 24
Peak memory 198648 kb
Host smart-9ac2fce8-bb03-479a-af5b-adc68e25f893
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656250066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3656250066
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3157909533
Short name T580
Test name
Test status
Simulation time 155432205 ps
CPU time 1.55 seconds
Started Jul 09 04:38:03 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 198368 kb
Host smart-7907650f-06cf-4d3e-b85c-1e349e946f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157909533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3157909533
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.843416630
Short name T49
Test name
Test status
Simulation time 34730817 ps
CPU time 1 seconds
Started Jul 09 04:38:02 PM PDT 24
Finished Jul 09 04:38:04 PM PDT 24
Peak memory 196152 kb
Host smart-cfb47516-758e-4fab-b610-7ade9c7f175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843416630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.843416630
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.676034133
Short name T613
Test name
Test status
Simulation time 187911431 ps
CPU time 1.28 seconds
Started Jul 09 04:38:11 PM PDT 24
Finished Jul 09 04:38:13 PM PDT 24
Peak memory 196800 kb
Host smart-5336467f-e83b-41ce-9222-309e109dd5fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676034133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.676034133
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2742240491
Short name T197
Test name
Test status
Simulation time 21322200817 ps
CPU time 80.01 seconds
Started Jul 09 04:38:04 PM PDT 24
Finished Jul 09 04:39:25 PM PDT 24
Peak memory 198736 kb
Host smart-9400a909-bd28-4fcc-bb58-0239f20c5402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742240491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2742240491
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2282233939
Short name T24
Test name
Test status
Simulation time 76734020431 ps
CPU time 1561.22 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 05:04:09 PM PDT 24
Peak memory 198816 kb
Host smart-ee753a1f-99fc-461b-8015-1068d30c9352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2282233939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2282233939
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.16478299
Short name T281
Test name
Test status
Simulation time 15584013 ps
CPU time 0.6 seconds
Started Jul 09 04:38:03 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 194544 kb
Host smart-8fab4d6f-23de-402b-a8ad-45f55ca13e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16478299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.16478299
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1910395271
Short name T18
Test name
Test status
Simulation time 53715972 ps
CPU time 0.69 seconds
Started Jul 09 04:38:01 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 196100 kb
Host smart-dc175995-326f-4185-9f55-51fb9b25f988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910395271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1910395271
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1601357287
Short name T614
Test name
Test status
Simulation time 236350515 ps
CPU time 8.48 seconds
Started Jul 09 04:38:02 PM PDT 24
Finished Jul 09 04:38:11 PM PDT 24
Peak memory 198552 kb
Host smart-e5d711dd-8c78-45e4-9487-c491c2e1cc59
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601357287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1601357287
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4138972977
Short name T131
Test name
Test status
Simulation time 60797649 ps
CPU time 0.62 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 194952 kb
Host smart-26c83017-e70d-451a-99c3-9b113bb1d529
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138972977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4138972977
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4043393113
Short name T401
Test name
Test status
Simulation time 132677963 ps
CPU time 0.83 seconds
Started Jul 09 04:38:02 PM PDT 24
Finished Jul 09 04:38:04 PM PDT 24
Peak memory 196000 kb
Host smart-940e80a3-69aa-4f20-866a-19725c92485d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043393113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4043393113
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2348511459
Short name T298
Test name
Test status
Simulation time 354417840 ps
CPU time 3.39 seconds
Started Jul 09 04:38:04 PM PDT 24
Finished Jul 09 04:38:08 PM PDT 24
Peak memory 198636 kb
Host smart-ab8a89b4-1788-41a6-843d-ecee43f8bda8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348511459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2348511459
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2696398542
Short name T417
Test name
Test status
Simulation time 791548482 ps
CPU time 3.63 seconds
Started Jul 09 04:38:08 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 198584 kb
Host smart-ca4adeeb-0619-45c9-8b55-507371f12958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696398542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2696398542
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.238463350
Short name T290
Test name
Test status
Simulation time 109090811 ps
CPU time 0.77 seconds
Started Jul 09 04:38:05 PM PDT 24
Finished Jul 09 04:38:06 PM PDT 24
Peak memory 196040 kb
Host smart-ee44ead6-1d74-4214-a035-d935f5cf4ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238463350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.238463350
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1152304600
Short name T89
Test name
Test status
Simulation time 54524574 ps
CPU time 1.01 seconds
Started Jul 09 04:38:03 PM PDT 24
Finished Jul 09 04:38:05 PM PDT 24
Peak memory 196484 kb
Host smart-606956b3-5a45-49a4-9c57-8bc4a02db55a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152304600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1152304600
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1278637207
Short name T520
Test name
Test status
Simulation time 1202676864 ps
CPU time 4.76 seconds
Started Jul 09 04:38:06 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 198624 kb
Host smart-1e2e8650-c25d-4e03-b44d-878185db5bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278637207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1278637207
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4230723194
Short name T155
Test name
Test status
Simulation time 178479572 ps
CPU time 0.82 seconds
Started Jul 09 04:38:06 PM PDT 24
Finished Jul 09 04:38:07 PM PDT 24
Peak memory 196468 kb
Host smart-1c5cef3a-3eb7-4d78-9a0e-cfd7d5d34ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230723194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4230723194
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.889918880
Short name T345
Test name
Test status
Simulation time 60154112 ps
CPU time 1.15 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 196116 kb
Host smart-e65105b6-e6fd-4e59-8b7d-378dad3fd416
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889918880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.889918880
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.700501337
Short name T592
Test name
Test status
Simulation time 87886509128 ps
CPU time 185.09 seconds
Started Jul 09 04:38:07 PM PDT 24
Finished Jul 09 04:41:14 PM PDT 24
Peak memory 198656 kb
Host smart-10697ce3-2080-481b-95cd-155d1432c44b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700501337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.700501337
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2396999988
Short name T916
Test name
Test status
Simulation time 174811768 ps
CPU time 1.51 seconds
Started Jul 09 05:04:14 PM PDT 24
Finished Jul 09 05:04:16 PM PDT 24
Peak memory 196712 kb
Host smart-d8740282-a274-4073-8453-e19f93843186
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2396999988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2396999988
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3562432209
Short name T941
Test name
Test status
Simulation time 212072542 ps
CPU time 1.1 seconds
Started Jul 09 05:04:08 PM PDT 24
Finished Jul 09 05:04:10 PM PDT 24
Peak memory 197648 kb
Host smart-2d559e0f-686c-43b5-b389-f9413a7fdb45
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562432209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3562432209
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.768308169
Short name T914
Test name
Test status
Simulation time 138689112 ps
CPU time 1.08 seconds
Started Jul 09 05:04:13 PM PDT 24
Finished Jul 09 05:04:15 PM PDT 24
Peak memory 196860 kb
Host smart-9c8fd18d-0050-40d8-810c-82a65969d141
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=768308169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.768308169
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127537737
Short name T915
Test name
Test status
Simulation time 84039474 ps
CPU time 1.05 seconds
Started Jul 09 05:04:11 PM PDT 24
Finished Jul 09 05:04:13 PM PDT 24
Peak memory 197024 kb
Host smart-0e2b6b45-75bf-4a72-af85-ef8033e803bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127537737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.127537737
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.626891780
Short name T945
Test name
Test status
Simulation time 81322026 ps
CPU time 1.41 seconds
Started Jul 09 05:04:16 PM PDT 24
Finished Jul 09 05:04:18 PM PDT 24
Peak memory 196888 kb
Host smart-d00faef8-8637-467d-bc8b-fb3dd7053a99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=626891780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.626891780
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2907838163
Short name T918
Test name
Test status
Simulation time 41417591 ps
CPU time 1.28 seconds
Started Jul 09 05:04:11 PM PDT 24
Finished Jul 09 05:04:14 PM PDT 24
Peak memory 195988 kb
Host smart-32b40498-2928-4e52-b11a-72aa983d56bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907838163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2907838163
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4006715918
Short name T862
Test name
Test status
Simulation time 57693252 ps
CPU time 1.5 seconds
Started Jul 09 05:04:14 PM PDT 24
Finished Jul 09 05:04:16 PM PDT 24
Peak memory 196940 kb
Host smart-3b6f4a80-a82a-4759-81cf-0f035412b445
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4006715918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4006715918
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458582222
Short name T931
Test name
Test status
Simulation time 115111997 ps
CPU time 0.84 seconds
Started Jul 09 05:04:13 PM PDT 24
Finished Jul 09 05:04:15 PM PDT 24
Peak memory 196360 kb
Host smart-9f747032-54bf-4fe6-ab92-706e37c78862
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458582222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2458582222
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2138608979
Short name T909
Test name
Test status
Simulation time 76205776 ps
CPU time 1.37 seconds
Started Jul 09 05:04:15 PM PDT 24
Finished Jul 09 05:04:17 PM PDT 24
Peak memory 196892 kb
Host smart-cc44959f-7fbd-4089-baba-0e4d4e144d78
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2138608979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2138608979
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3764888712
Short name T920
Test name
Test status
Simulation time 58788050 ps
CPU time 1.57 seconds
Started Jul 09 05:04:16 PM PDT 24
Finished Jul 09 05:04:18 PM PDT 24
Peak memory 196888 kb
Host smart-f4f3728d-6b25-4f54-8d4f-e4b2f168631c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764888712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3764888712
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1037566911
Short name T849
Test name
Test status
Simulation time 46624443 ps
CPU time 0.88 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 196568 kb
Host smart-9b3aacda-8972-4145-9aee-267c6bc539a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1037566911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1037566911
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123782401
Short name T871
Test name
Test status
Simulation time 30525552 ps
CPU time 1.05 seconds
Started Jul 09 05:04:14 PM PDT 24
Finished Jul 09 05:04:16 PM PDT 24
Peak memory 196840 kb
Host smart-069a6903-c9ad-4dfb-98fd-1f1673aeaccf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123782401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2123782401
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3969141202
Short name T858
Test name
Test status
Simulation time 43110118 ps
CPU time 0.92 seconds
Started Jul 09 05:04:12 PM PDT 24
Finished Jul 09 05:04:14 PM PDT 24
Peak memory 196760 kb
Host smart-39583bd5-baa1-4bbc-bea0-3f9152fed4bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3969141202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3969141202
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3214801071
Short name T872
Test name
Test status
Simulation time 34559914 ps
CPU time 0.98 seconds
Started Jul 09 05:04:14 PM PDT 24
Finished Jul 09 05:04:15 PM PDT 24
Peak memory 196196 kb
Host smart-b3e13492-b200-44a0-bdf5-c1f13a2d76f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214801071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3214801071
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1307927727
Short name T866
Test name
Test status
Simulation time 183730447 ps
CPU time 1.11 seconds
Started Jul 09 05:04:13 PM PDT 24
Finished Jul 09 05:04:16 PM PDT 24
Peak memory 196888 kb
Host smart-410f6b23-d791-4610-a550-ffce834befcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1307927727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1307927727
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4018164964
Short name T896
Test name
Test status
Simulation time 338879639 ps
CPU time 1.18 seconds
Started Jul 09 05:04:13 PM PDT 24
Finished Jul 09 05:04:16 PM PDT 24
Peak memory 198312 kb
Host smart-e684966a-30c4-4b14-bd9a-99c93d43803e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018164964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4018164964
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.793372818
Short name T943
Test name
Test status
Simulation time 125904125 ps
CPU time 1.28 seconds
Started Jul 09 05:04:14 PM PDT 24
Finished Jul 09 05:04:16 PM PDT 24
Peak memory 198336 kb
Host smart-90804450-2103-4ab1-9ad6-514110cf7b3d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=793372818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.793372818
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1594113033
Short name T882
Test name
Test status
Simulation time 325002000 ps
CPU time 1.06 seconds
Started Jul 09 05:04:13 PM PDT 24
Finished Jul 09 05:04:15 PM PDT 24
Peak memory 197040 kb
Host smart-e4027631-67eb-4429-9e2a-44d732ee7fe0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594113033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1594113033
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1831525363
Short name T934
Test name
Test status
Simulation time 49534935 ps
CPU time 1.15 seconds
Started Jul 09 05:04:15 PM PDT 24
Finished Jul 09 05:04:17 PM PDT 24
Peak memory 196864 kb
Host smart-78ca88bd-96ed-43dc-aa6e-8d0d3b7eb1c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1831525363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1831525363
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2436169681
Short name T853
Test name
Test status
Simulation time 40984364 ps
CPU time 1.21 seconds
Started Jul 09 05:04:14 PM PDT 24
Finished Jul 09 05:04:16 PM PDT 24
Peak memory 196928 kb
Host smart-46344a59-8f0f-495a-bfd8-025ca794c86e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436169681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2436169681
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2328335560
Short name T938
Test name
Test status
Simulation time 664196272 ps
CPU time 1.3 seconds
Started Jul 09 05:04:12 PM PDT 24
Finished Jul 09 05:04:15 PM PDT 24
Peak memory 198364 kb
Host smart-bfbe93a8-d8c8-40de-bad1-f9b9f7df327f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2328335560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2328335560
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.979512517
Short name T875
Test name
Test status
Simulation time 212995700 ps
CPU time 1.4 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:28 PM PDT 24
Peak memory 196940 kb
Host smart-7e0a3bfe-eba1-425f-908a-d921ec3251e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979512517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.979512517
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2449092451
Short name T891
Test name
Test status
Simulation time 45935444 ps
CPU time 1.04 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:22 PM PDT 24
Peak memory 198256 kb
Host smart-a620e85b-e922-4c1b-86a9-dc683e8b7c12
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2449092451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2449092451
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1705269345
Short name T908
Test name
Test status
Simulation time 84162887 ps
CPU time 1.09 seconds
Started Jul 09 05:04:17 PM PDT 24
Finished Jul 09 05:04:19 PM PDT 24
Peak memory 196876 kb
Host smart-3649a87d-3622-45ff-847b-c11166abe507
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705269345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1705269345
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2469663200
Short name T865
Test name
Test status
Simulation time 49729807 ps
CPU time 1.34 seconds
Started Jul 09 05:04:10 PM PDT 24
Finished Jul 09 05:04:12 PM PDT 24
Peak memory 196820 kb
Host smart-e10f88dd-d254-4f37-bbc1-c12a6d684bb2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2469663200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2469663200
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59705379
Short name T928
Test name
Test status
Simulation time 367614855 ps
CPU time 1.6 seconds
Started Jul 09 05:04:11 PM PDT 24
Finished Jul 09 05:04:13 PM PDT 24
Peak memory 197024 kb
Host smart-924124ce-0bae-4a62-8c41-2a47c1e35a3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59705379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.59705379
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1270613631
Short name T939
Test name
Test status
Simulation time 272035814 ps
CPU time 1.1 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 198180 kb
Host smart-ce243ef1-7843-46d5-a9b4-c939984c116b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1270613631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1270613631
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3164248041
Short name T867
Test name
Test status
Simulation time 95691391 ps
CPU time 1.41 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 197632 kb
Host smart-e6faa5af-e737-4858-9bf1-944569a49724
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164248041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3164248041
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3650203726
Short name T890
Test name
Test status
Simulation time 365235460 ps
CPU time 1.28 seconds
Started Jul 09 05:04:21 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 196080 kb
Host smart-36e871dd-c2b7-4ed4-9bf9-a4555ddeaf13
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3650203726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3650203726
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305150446
Short name T873
Test name
Test status
Simulation time 146219021 ps
CPU time 0.93 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:21 PM PDT 24
Peak memory 195676 kb
Host smart-faf8ec00-7e60-44bc-a6c7-ce1eabee9c5d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305150446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3305150446
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3251166886
Short name T885
Test name
Test status
Simulation time 47236528 ps
CPU time 1.45 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:22 PM PDT 24
Peak memory 197076 kb
Host smart-da1ebafb-abc3-43af-8a9c-1f8eea07392c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3251166886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3251166886
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1075535816
Short name T855
Test name
Test status
Simulation time 166203914 ps
CPU time 1 seconds
Started Jul 09 05:04:22 PM PDT 24
Finished Jul 09 05:04:24 PM PDT 24
Peak memory 196836 kb
Host smart-c0108ee2-d197-4bf1-ab46-1fe085f206ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075535816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1075535816
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2323052612
Short name T897
Test name
Test status
Simulation time 194063861 ps
CPU time 1.51 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 196896 kb
Host smart-80ef71b7-9250-4eb9-825e-c6db1f372eda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2323052612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2323052612
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.941300522
Short name T863
Test name
Test status
Simulation time 54513997 ps
CPU time 1.05 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:21 PM PDT 24
Peak memory 196904 kb
Host smart-11de5d58-d4d6-4fab-826f-f1643f21a449
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941300522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.941300522
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.54044941
Short name T902
Test name
Test status
Simulation time 180995996 ps
CPU time 1.6 seconds
Started Jul 09 05:04:21 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 198368 kb
Host smart-e9a56b35-1639-420d-be5c-afc1fb4829ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=54044941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.54044941
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2659150893
Short name T877
Test name
Test status
Simulation time 212551385 ps
CPU time 1.27 seconds
Started Jul 09 05:04:27 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 196824 kb
Host smart-99d5db29-4929-45e4-89c6-62a8d71d93c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659150893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2659150893
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2186303807
Short name T942
Test name
Test status
Simulation time 166194475 ps
CPU time 1.55 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:22 PM PDT 24
Peak memory 197156 kb
Host smart-5bdbb97a-42d1-43a6-93bf-de3245283fa0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2186303807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2186303807
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3426578299
Short name T857
Test name
Test status
Simulation time 40756716 ps
CPU time 1.06 seconds
Started Jul 09 05:04:22 PM PDT 24
Finished Jul 09 05:04:24 PM PDT 24
Peak memory 191996 kb
Host smart-2e707826-9925-417e-b840-d903b60cfcf7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426578299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3426578299
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3030130444
Short name T848
Test name
Test status
Simulation time 60236498 ps
CPU time 1.2 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:21 PM PDT 24
Peak memory 197184 kb
Host smart-5023251e-8674-411e-83ff-b82074c9d870
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3030130444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3030130444
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3156376158
Short name T905
Test name
Test status
Simulation time 86656312 ps
CPU time 1.36 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:31 PM PDT 24
Peak memory 198268 kb
Host smart-160b7545-4bc9-4ab7-a0f2-e948976d2529
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156376158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3156376158
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.183488789
Short name T861
Test name
Test status
Simulation time 47047541 ps
CPU time 0.9 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 196512 kb
Host smart-18405d93-b46a-4069-ba5c-bdc9aa0dc413
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=183488789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.183488789
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301571145
Short name T874
Test name
Test status
Simulation time 74475366 ps
CPU time 1.53 seconds
Started Jul 09 05:04:17 PM PDT 24
Finished Jul 09 05:04:19 PM PDT 24
Peak memory 198536 kb
Host smart-4a298b08-0a08-4846-b4a7-55cde3e9b746
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301571145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2301571145
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3862046380
Short name T926
Test name
Test status
Simulation time 72920011 ps
CPU time 1.2 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 196848 kb
Host smart-f0be8fc8-d70a-4c4a-9791-74c072030cee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3862046380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3862046380
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2573017372
Short name T919
Test name
Test status
Simulation time 174401833 ps
CPU time 1.2 seconds
Started Jul 09 05:04:17 PM PDT 24
Finished Jul 09 05:04:18 PM PDT 24
Peak memory 197644 kb
Host smart-d98a27a8-912f-46ab-a531-e503cdf5ff66
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573017372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2573017372
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.693302043
Short name T864
Test name
Test status
Simulation time 115179429 ps
CPU time 1.31 seconds
Started Jul 09 05:04:18 PM PDT 24
Finished Jul 09 05:04:20 PM PDT 24
Peak memory 196984 kb
Host smart-75c62fe4-c30a-42d9-ae42-7f609665b4a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=693302043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.693302043
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2581950739
Short name T935
Test name
Test status
Simulation time 48832617 ps
CPU time 1.01 seconds
Started Jul 09 05:04:18 PM PDT 24
Finished Jul 09 05:04:19 PM PDT 24
Peak memory 198148 kb
Host smart-732a71df-8cf9-4c6a-96a7-47d00dc0506a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581950739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2581950739
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3847585525
Short name T924
Test name
Test status
Simulation time 304793887 ps
CPU time 1.39 seconds
Started Jul 09 05:04:09 PM PDT 24
Finished Jul 09 05:04:11 PM PDT 24
Peak memory 196872 kb
Host smart-6444a99b-f02e-4d7d-80c2-cefc7fc2c947
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3847585525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3847585525
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1579615483
Short name T886
Test name
Test status
Simulation time 24100676 ps
CPU time 0.99 seconds
Started Jul 09 05:04:08 PM PDT 24
Finished Jul 09 05:04:09 PM PDT 24
Peak memory 196776 kb
Host smart-8f402653-7bc8-4d37-af6a-4d40072384ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579615483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1579615483
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2100686077
Short name T921
Test name
Test status
Simulation time 65799327 ps
CPU time 1.22 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:21 PM PDT 24
Peak memory 198412 kb
Host smart-45858086-3380-4c8f-9885-29dec1731c24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2100686077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2100686077
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2989609361
Short name T923
Test name
Test status
Simulation time 191835689 ps
CPU time 1.06 seconds
Started Jul 09 05:04:21 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 196880 kb
Host smart-2a640b6f-d472-47ca-a761-9c0cf76a725b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989609361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2989609361
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.549036129
Short name T889
Test name
Test status
Simulation time 76469144 ps
CPU time 1.44 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 196884 kb
Host smart-34bf3da7-867a-412f-93a7-704ebd3606e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=549036129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.549036129
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.912017456
Short name T933
Test name
Test status
Simulation time 193803015 ps
CPU time 1.58 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 196896 kb
Host smart-9af1bb05-7f3c-43f9-adb3-50261f6c7153
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912017456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.912017456
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2652957139
Short name T937
Test name
Test status
Simulation time 41465433 ps
CPU time 1.3 seconds
Started Jul 09 05:04:18 PM PDT 24
Finished Jul 09 05:04:20 PM PDT 24
Peak memory 196884 kb
Host smart-927137f9-bc4d-40b0-8c3e-6f0bb89de63c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2652957139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2652957139
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2889290997
Short name T852
Test name
Test status
Simulation time 334551464 ps
CPU time 1.14 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:21 PM PDT 24
Peak memory 196956 kb
Host smart-190acf7d-902e-43e3-91eb-f561c50e1ecd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889290997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2889290997
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1868049778
Short name T883
Test name
Test status
Simulation time 152425594 ps
CPU time 1.09 seconds
Started Jul 09 05:04:21 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 198284 kb
Host smart-f3399432-080d-477c-8a92-94df3e172e14
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1868049778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1868049778
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4231181283
Short name T893
Test name
Test status
Simulation time 102868390 ps
CPU time 0.88 seconds
Started Jul 09 05:04:16 PM PDT 24
Finished Jul 09 05:04:18 PM PDT 24
Peak memory 195848 kb
Host smart-4c91dc88-6021-49ad-a562-3b65d6927733
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231181283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4231181283
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1201548185
Short name T878
Test name
Test status
Simulation time 96546981 ps
CPU time 1.18 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:22 PM PDT 24
Peak memory 196244 kb
Host smart-e1f1ab08-39d6-4e21-8c44-d3d20c721001
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1201548185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1201548185
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3745589469
Short name T860
Test name
Test status
Simulation time 61153069 ps
CPU time 1.33 seconds
Started Jul 09 05:04:18 PM PDT 24
Finished Jul 09 05:04:20 PM PDT 24
Peak memory 196288 kb
Host smart-25de328f-fa59-4a0a-8820-5cb8383b049c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745589469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3745589469
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1844303948
Short name T912
Test name
Test status
Simulation time 162314941 ps
CPU time 0.92 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:20 PM PDT 24
Peak memory 195632 kb
Host smart-c190b6e0-9650-4157-bdcb-6ec3f3a7ac1f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1844303948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1844303948
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4203061644
Short name T879
Test name
Test status
Simulation time 112652643 ps
CPU time 0.84 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:21 PM PDT 24
Peak memory 195680 kb
Host smart-00aff7d5-1256-47a7-9dc9-d15525af4861
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203061644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4203061644
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1558393940
Short name T870
Test name
Test status
Simulation time 377383347 ps
CPU time 1.54 seconds
Started Jul 09 05:04:16 PM PDT 24
Finished Jul 09 05:04:18 PM PDT 24
Peak memory 197028 kb
Host smart-4646f23b-2283-455a-9b5a-c3bffe2d44a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1558393940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1558393940
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.234051043
Short name T869
Test name
Test status
Simulation time 303608693 ps
CPU time 1.57 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:22 PM PDT 24
Peak memory 197096 kb
Host smart-dc313657-719b-4975-b5ac-0742dca4417f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234051043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.234051043
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3735387390
Short name T899
Test name
Test status
Simulation time 125561440 ps
CPU time 0.82 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 195724 kb
Host smart-e2edf7bd-8267-473c-b072-84a2c3312960
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3735387390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3735387390
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4242274857
Short name T906
Test name
Test status
Simulation time 116336260 ps
CPU time 1.01 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 196132 kb
Host smart-3ed54f02-9e28-4fee-aab0-4e53c84730e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242274857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4242274857
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2237832249
Short name T910
Test name
Test status
Simulation time 92636171 ps
CPU time 1.4 seconds
Started Jul 09 05:04:19 PM PDT 24
Finished Jul 09 05:04:20 PM PDT 24
Peak memory 198344 kb
Host smart-b5c2b259-06e9-4abc-9544-037d3dcd74c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2237832249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2237832249
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1850237086
Short name T876
Test name
Test status
Simulation time 23574845 ps
CPU time 0.83 seconds
Started Jul 09 05:04:22 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 195684 kb
Host smart-e6bd1921-b6a2-45cd-b037-688bed11d2c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850237086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1850237086
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1869691523
Short name T901
Test name
Test status
Simulation time 132454430 ps
CPU time 1 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 196864 kb
Host smart-7fcd972e-79c7-4075-940a-2db9072bb830
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1869691523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1869691523
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3339404416
Short name T927
Test name
Test status
Simulation time 46076068 ps
CPU time 1.04 seconds
Started Jul 09 05:04:21 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 196744 kb
Host smart-429295bf-640b-45ff-bb05-feafafd4da22
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339404416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3339404416
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3230241509
Short name T847
Test name
Test status
Simulation time 152759870 ps
CPU time 1.03 seconds
Started Jul 09 05:04:09 PM PDT 24
Finished Jul 09 05:04:11 PM PDT 24
Peak memory 196900 kb
Host smart-f8f9b352-7f60-4a66-85f7-65c693d714b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3230241509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3230241509
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1719396896
Short name T903
Test name
Test status
Simulation time 29190658 ps
CPU time 1.1 seconds
Started Jul 09 05:04:12 PM PDT 24
Finished Jul 09 05:04:15 PM PDT 24
Peak memory 197648 kb
Host smart-1e4ef39e-0c27-4cd1-8d5a-74bf14312214
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719396896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1719396896
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.703651857
Short name T892
Test name
Test status
Simulation time 237011703 ps
CPU time 1.28 seconds
Started Jul 09 05:04:21 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 197116 kb
Host smart-f4e54bb9-b99f-43b3-aad4-ea383be2482b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=703651857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.703651857
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1668974061
Short name T895
Test name
Test status
Simulation time 113476498 ps
CPU time 0.92 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:27 PM PDT 24
Peak memory 196560 kb
Host smart-0bb44d8f-7ed6-4c82-9558-20554da9a34a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668974061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1668974061
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3975801746
Short name T946
Test name
Test status
Simulation time 154399965 ps
CPU time 1.33 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:29 PM PDT 24
Peak memory 198180 kb
Host smart-541d6684-90db-49e7-8df6-e453cdf357a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3975801746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3975801746
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574055687
Short name T936
Test name
Test status
Simulation time 275569394 ps
CPU time 0.8 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:28 PM PDT 24
Peak memory 196292 kb
Host smart-d8d9cc0e-2d98-4580-88b3-3b43dba7540c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574055687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.574055687
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1015441043
Short name T880
Test name
Test status
Simulation time 340868624 ps
CPU time 1.15 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 196912 kb
Host smart-7334cb36-56f8-4b1c-bdd2-3d9a8119a8db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1015441043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1015441043
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1155317819
Short name T925
Test name
Test status
Simulation time 85477724 ps
CPU time 1.4 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 198416 kb
Host smart-b15e4e0c-8872-4ee3-a9cc-46e6b97f40bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155317819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1155317819
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.710980273
Short name T922
Test name
Test status
Simulation time 49207407 ps
CPU time 1.24 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 196684 kb
Host smart-674be5b1-816a-4b4f-99b8-f338172b82b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=710980273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.710980273
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.296767465
Short name T881
Test name
Test status
Simulation time 80019574 ps
CPU time 1.04 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 196180 kb
Host smart-4e0ca496-6adc-4434-935f-6f60b5ce644b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296767465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.296767465
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1069211161
Short name T932
Test name
Test status
Simulation time 37377238 ps
CPU time 0.97 seconds
Started Jul 09 05:04:22 PM PDT 24
Finished Jul 09 05:04:24 PM PDT 24
Peak memory 195936 kb
Host smart-8a81479c-9a9c-4bb0-945a-0d9fbcb8ad70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1069211161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1069211161
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3413951025
Short name T944
Test name
Test status
Simulation time 591637514 ps
CPU time 1.11 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 198372 kb
Host smart-fb14c569-a8cd-4d22-8b32-057b82ae9454
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413951025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3413951025
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4173840989
Short name T856
Test name
Test status
Simulation time 31881676 ps
CPU time 0.92 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:22 PM PDT 24
Peak memory 196824 kb
Host smart-55dcb831-3d4e-4093-b2cc-859d876720aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4173840989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4173840989
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3064602884
Short name T854
Test name
Test status
Simulation time 65819772 ps
CPU time 1.47 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 197148 kb
Host smart-9bb821f6-8840-4c7f-b339-7d3af044c580
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064602884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3064602884
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1194759091
Short name T900
Test name
Test status
Simulation time 66770001 ps
CPU time 1.01 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 196212 kb
Host smart-255027e6-d2d5-4b5f-b949-85ec3b0cb4b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1194759091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1194759091
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1712829953
Short name T894
Test name
Test status
Simulation time 128661491 ps
CPU time 1.28 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 197144 kb
Host smart-6371f2b1-37f0-4097-98be-954a10deb84e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712829953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1712829953
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2176702281
Short name T850
Test name
Test status
Simulation time 73322034 ps
CPU time 1.05 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 198672 kb
Host smart-57c445f5-6a0d-47ba-8a71-65b04c75ff66
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2176702281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2176702281
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1069500071
Short name T930
Test name
Test status
Simulation time 42921541 ps
CPU time 1.38 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:28 PM PDT 24
Peak memory 196920 kb
Host smart-d9d56d8d-7cdd-4d0b-b63e-88f128e2f304
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069500071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1069500071
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1865570808
Short name T929
Test name
Test status
Simulation time 394151949 ps
CPU time 1.3 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 196944 kb
Host smart-bedb42ce-5c4e-4d1d-862c-cc55422ea926
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1865570808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1865570808
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4078605209
Short name T907
Test name
Test status
Simulation time 172152753 ps
CPU time 1.6 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:27 PM PDT 24
Peak memory 196924 kb
Host smart-0c7fd78a-354f-4157-b7a1-b040b562c679
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078605209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4078605209
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4262200284
Short name T898
Test name
Test status
Simulation time 182759756 ps
CPU time 1.09 seconds
Started Jul 09 05:04:20 PM PDT 24
Finished Jul 09 05:04:23 PM PDT 24
Peak memory 196796 kb
Host smart-699a6d75-6bbe-4ea9-abdd-c857413c1003
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4262200284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4262200284
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4096912523
Short name T911
Test name
Test status
Simulation time 86285158 ps
CPU time 0.92 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:27 PM PDT 24
Peak memory 195584 kb
Host smart-805a4a48-402b-4935-83f8-385e9cb3ee97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096912523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4096912523
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.544662080
Short name T851
Test name
Test status
Simulation time 253735497 ps
CPU time 1.17 seconds
Started Jul 09 05:04:08 PM PDT 24
Finished Jul 09 05:04:10 PM PDT 24
Peak memory 196860 kb
Host smart-ddf98ab1-2e65-430f-930b-a06b5c8b6459
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=544662080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.544662080
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2317467829
Short name T904
Test name
Test status
Simulation time 64868637 ps
CPU time 1.65 seconds
Started Jul 09 05:04:09 PM PDT 24
Finished Jul 09 05:04:11 PM PDT 24
Peak memory 198288 kb
Host smart-3e2c30e9-0975-40a6-8a3f-bf4d52f29085
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317467829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2317467829
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3198944240
Short name T913
Test name
Test status
Simulation time 47260265 ps
CPU time 0.89 seconds
Started Jul 09 05:04:11 PM PDT 24
Finished Jul 09 05:04:13 PM PDT 24
Peak memory 195876 kb
Host smart-694da5a3-783d-4cb3-b393-babd2e84b145
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3198944240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3198944240
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725678255
Short name T940
Test name
Test status
Simulation time 40753993 ps
CPU time 0.89 seconds
Started Jul 09 05:04:11 PM PDT 24
Finished Jul 09 05:04:13 PM PDT 24
Peak memory 195860 kb
Host smart-b1f78ba1-55d8-4e3e-a1cc-e7e239d08efc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725678255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3725678255
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1729768845
Short name T917
Test name
Test status
Simulation time 394512713 ps
CPU time 1.47 seconds
Started Jul 09 05:04:10 PM PDT 24
Finished Jul 09 05:04:12 PM PDT 24
Peak memory 196980 kb
Host smart-a0183643-db02-45eb-aa9b-1a4bcaefbbf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1729768845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1729768845
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151716813
Short name T868
Test name
Test status
Simulation time 59748721 ps
CPU time 1.33 seconds
Started Jul 09 05:04:10 PM PDT 24
Finished Jul 09 05:04:12 PM PDT 24
Peak memory 196840 kb
Host smart-aa6704db-12d0-4e6a-b3ad-49078509d114
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151716813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1151716813
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1741647025
Short name T859
Test name
Test status
Simulation time 66299078 ps
CPU time 1.11 seconds
Started Jul 09 05:04:10 PM PDT 24
Finished Jul 09 05:04:12 PM PDT 24
Peak memory 196188 kb
Host smart-e459eea9-df36-485b-8fda-8bb5fed12d57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1741647025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1741647025
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2997775409
Short name T884
Test name
Test status
Simulation time 91208951 ps
CPU time 1.05 seconds
Started Jul 09 05:04:09 PM PDT 24
Finished Jul 09 05:04:11 PM PDT 24
Peak memory 196884 kb
Host smart-457011ef-1b76-4bf4-bc87-f94e1ad76a25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997775409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2997775409
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2943384390
Short name T887
Test name
Test status
Simulation time 168335196 ps
CPU time 1.02 seconds
Started Jul 09 05:04:16 PM PDT 24
Finished Jul 09 05:04:18 PM PDT 24
Peak memory 196028 kb
Host smart-da25712e-2ba1-4c14-a75a-e911886429b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2943384390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2943384390
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1317312796
Short name T888
Test name
Test status
Simulation time 101043384 ps
CPU time 1.5 seconds
Started Jul 09 05:04:12 PM PDT 24
Finished Jul 09 05:04:14 PM PDT 24
Peak memory 196924 kb
Host smart-1702f27d-0954-4c0a-8cb5-e458c3fc9ec8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317312796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1317312796
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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