Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5470840	1			T22	1		T23	66		T24	234
all_pins[1]	5470840	1			T22	1		T23	66		T24	234
all_pins[2]	5470840	1			T22	1		T23	66		T24	234
all_pins[3]	5470840	1			T22	1		T23	66		T24	234
all_pins[4]	5470840	1			T22	1		T23	66		T24	234
all_pins[5]	5470840	1			T22	1		T23	66		T24	234
all_pins[6]	5470840	1			T22	1		T23	66		T24	234
all_pins[7]	5470840	1			T22	1		T23	66		T24	234
all_pins[8]	5470840	1			T22	1		T23	66		T24	234
all_pins[9]	5470840	1			T22	1		T23	66		T24	234
all_pins[10]	5470840	1			T22	1		T23	66		T24	234
all_pins[11]	5470840	1			T22	1		T23	66		T24	234
all_pins[12]	5470840	1			T22	1		T23	66		T24	234
all_pins[13]	5470840	1			T22	1		T23	66		T24	234
all_pins[14]	5470840	1			T22	1		T23	66		T24	234
all_pins[15]	5470840	1			T22	1		T23	66		T24	234
all_pins[16]	5470840	1			T22	1		T23	66		T24	234
all_pins[17]	5470840	1			T22	1		T23	66		T24	234
all_pins[18]	5470840	1			T22	1		T23	66		T24	234
all_pins[19]	5470840	1			T22	1		T23	66		T24	234
all_pins[20]	5470840	1			T22	1		T23	66		T24	234
all_pins[21]	5470840	1			T22	1		T23	66		T24	234
all_pins[22]	5470840	1			T22	1		T23	66		T24	234
all_pins[23]	5470840	1			T22	1		T23	66		T24	234
all_pins[24]	5470840	1			T22	1		T23	66		T24	234
all_pins[25]	5470840	1			T22	1		T23	66		T24	234
all_pins[26]	5470840	1			T22	1		T23	66		T24	234
all_pins[27]	5470840	1			T22	1		T23	66		T24	234
all_pins[28]	5470840	1			T22	1		T23	66		T24	234
all_pins[29]	5470840	1			T22	1		T23	66		T24	234
all_pins[30]	5470840	1			T22	1		T23	66		T24	234
all_pins[31]	5470840	1			T22	1		T23	66		T24	234

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	108742273	1			T22	32		T23	1055		T24	4667
values[0x1]	66324607	1			T23	1057		T24	2821		T29	1006
transitions[0x0=>0x1]	39764132	1			T23	525		T24	1733		T29	502
transitions[0x1=>0x0]	39763965	1			T23	524		T24	1733		T29	502

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3403621	1			T22	1		T23	41		T24	154
all_pins[0]	values[0x1]	2067219	1			T23	25		T24	80		T29	27
all_pins[0]	transitions[0x0=>0x1]	1278558	1			T23	12		T24	48		T29	14
all_pins[0]	transitions[0x1=>0x0]	1285455	1			T23	26		T24	60		T29	23
all_pins[1]	values[0x0]	3393264	1			T22	1		T23	33		T24	160
all_pins[1]	values[0x1]	2077576	1			T23	33		T24	74		T29	35
all_pins[1]	transitions[0x0=>0x1]	1243485	1			T23	20		T24	34		T29	17
all_pins[1]	transitions[0x1=>0x0]	1233128	1			T23	12		T24	40		T29	9
all_pins[2]	values[0x0]	3395727	1			T22	1		T23	33		T24	145
all_pins[2]	values[0x1]	2075113	1			T23	33		T24	89		T29	29
all_pins[2]	transitions[0x0=>0x1]	1240056	1			T23	15		T24	65		T29	14
all_pins[2]	transitions[0x1=>0x0]	1242519	1			T23	15		T24	50		T29	20
all_pins[3]	values[0x0]	3398749	1			T22	1		T23	40		T24	179
all_pins[3]	values[0x1]	2072091	1			T23	26		T24	55		T29	32
all_pins[3]	transitions[0x0=>0x1]	1239150	1			T23	11		T24	42		T29	15
all_pins[3]	transitions[0x1=>0x0]	1242172	1			T23	18		T24	76		T29	12
all_pins[4]	values[0x0]	3392994	1			T22	1		T23	33		T24	130
all_pins[4]	values[0x1]	2077846	1			T23	33		T24	104		T29	35
all_pins[4]	transitions[0x0=>0x1]	1243535	1			T23	22		T24	77		T29	16
all_pins[4]	transitions[0x1=>0x0]	1237780	1			T23	15		T24	28		T29	13
all_pins[5]	values[0x0]	3397926	1			T22	1		T23	22		T24	146
all_pins[5]	values[0x1]	2072914	1			T23	44		T24	88		T29	25
all_pins[5]	transitions[0x0=>0x1]	1241003	1			T23	20		T24	59		T29	7
all_pins[5]	transitions[0x1=>0x0]	1245935	1			T23	9		T24	75		T29	17
all_pins[6]	values[0x0]	3390335	1			T22	1		T23	31		T24	173
all_pins[6]	values[0x1]	2080505	1			T23	35		T24	61		T29	37
all_pins[6]	transitions[0x0=>0x1]	1246488	1			T23	9		T24	35		T29	22
all_pins[6]	transitions[0x1=>0x0]	1238897	1			T23	18		T24	62		T29	10
all_pins[7]	values[0x0]	3401565	1			T22	1		T23	27		T24	181
all_pins[7]	values[0x1]	2069275	1			T23	39		T24	53		T29	28
all_pins[7]	transitions[0x0=>0x1]	1234889	1			T23	15		T24	44		T29	11
all_pins[7]	transitions[0x1=>0x0]	1246119	1			T23	11		T24	52		T29	20
all_pins[8]	values[0x0]	3403374	1			T22	1		T23	28		T24	134
all_pins[8]	values[0x1]	2067466	1			T23	38		T24	100		T29	34
all_pins[8]	transitions[0x0=>0x1]	1239670	1			T23	18		T24	78		T29	15
all_pins[8]	transitions[0x1=>0x0]	1241479	1			T23	19		T24	31		T29	9
all_pins[9]	values[0x0]	3395134	1			T22	1		T23	35		T24	139
all_pins[9]	values[0x1]	2075706	1			T23	31		T24	95		T29	37
all_pins[9]	transitions[0x0=>0x1]	1244805	1			T23	11		T24	53		T29	16
all_pins[9]	transitions[0x1=>0x0]	1236565	1			T23	18		T24	58		T29	13
all_pins[10]	values[0x0]	3400785	1			T22	1		T23	28		T24	113
all_pins[10]	values[0x1]	2070055	1			T23	38		T24	121		T29	30
all_pins[10]	transitions[0x0=>0x1]	1240166	1			T23	23		T24	57		T29	15
all_pins[10]	transitions[0x1=>0x0]	1245817	1			T23	16		T24	31		T29	22
all_pins[11]	values[0x0]	3393164	1			T22	1		T23	40		T24	174
all_pins[11]	values[0x1]	2077676	1			T23	26		T24	60		T29	23
all_pins[11]	transitions[0x0=>0x1]	1246095	1			T23	12		T24	37		T29	11
all_pins[11]	transitions[0x1=>0x0]	1238474	1			T23	24		T24	98		T29	18
all_pins[12]	values[0x0]	3397319	1			T22	1		T23	35		T24	159
all_pins[12]	values[0x1]	2073521	1			T23	31		T24	75		T29	22
all_pins[12]	transitions[0x0=>0x1]	1238695	1			T23	19		T24	52		T29	14
all_pins[12]	transitions[0x1=>0x0]	1242850	1			T23	14		T24	37		T29	15
all_pins[13]	values[0x0]	3394661	1			T22	1		T23	27		T24	128
all_pins[13]	values[0x1]	2076179	1			T23	39		T24	106		T29	28
all_pins[13]	transitions[0x0=>0x1]	1244685	1			T23	19		T24	64		T29	22
all_pins[13]	transitions[0x1=>0x0]	1242027	1			T23	11		T24	33		T29	16
all_pins[14]	values[0x0]	3397808	1			T22	1		T23	26		T24	158
all_pins[14]	values[0x1]	2073032	1			T23	40		T24	76		T29	40
all_pins[14]	transitions[0x0=>0x1]	1239375	1			T23	19		T24	59		T29	22
all_pins[14]	transitions[0x1=>0x0]	1242522	1			T23	18		T24	89		T29	10
all_pins[15]	values[0x0]	3397039	1			T22	1		T23	36		T24	140
all_pins[15]	values[0x1]	2073801	1			T23	30		T24	94		T29	35
all_pins[15]	transitions[0x0=>0x1]	1239168	1			T23	13		T24	63		T29	14
all_pins[15]	transitions[0x1=>0x0]	1238399	1			T23	23		T24	45		T29	19
all_pins[16]	values[0x0]	3409637	1			T22	1		T23	38		T24	152
all_pins[16]	values[0x1]	2061203	1			T23	28		T24	82		T29	34
all_pins[16]	transitions[0x0=>0x1]	1236461	1			T23	16		T24	47		T29	13
all_pins[16]	transitions[0x1=>0x0]	1249059	1			T23	18		T24	59		T29	14
all_pins[17]	values[0x0]	3398310	1			T22	1		T23	34		T24	129
all_pins[17]	values[0x1]	2072530	1			T23	32		T24	105		T29	27
all_pins[17]	transitions[0x0=>0x1]	1246331	1			T23	16		T24	66		T29	11
all_pins[17]	transitions[0x1=>0x0]	1235004	1			T23	12		T24	43		T29	18
all_pins[18]	values[0x0]	3402263	1			T22	1		T23	36		T24	131
all_pins[18]	values[0x1]	2068577	1			T23	30		T24	103		T29	30
all_pins[18]	transitions[0x0=>0x1]	1238832	1			T23	18		T24	55		T29	15
all_pins[18]	transitions[0x1=>0x0]	1242785	1			T23	20		T24	57		T29	12
all_pins[19]	values[0x0]	3395623	1			T22	1		T23	32		T24	136
all_pins[19]	values[0x1]	2075217	1			T23	34		T24	98		T29	37
all_pins[19]	transitions[0x0=>0x1]	1244464	1			T23	17		T24	54		T29	20
all_pins[19]	transitions[0x1=>0x0]	1237824	1			T23	13		T24	59		T29	13
all_pins[20]	values[0x0]	3398751	1			T22	1		T23	37		T24	110
all_pins[20]	values[0x1]	2072089	1			T23	29		T24	124		T29	32
all_pins[20]	transitions[0x0=>0x1]	1238220	1			T23	13		T24	72		T29	13
all_pins[20]	transitions[0x1=>0x0]	1241348	1			T23	18		T24	46		T29	18
all_pins[21]	values[0x0]	3404224	1			T22	1		T23	38		T24	130
all_pins[21]	values[0x1]	2066616	1			T23	28		T24	104		T29	32
all_pins[21]	transitions[0x0=>0x1]	1239198	1			T23	16		T24	41		T29	17
all_pins[21]	transitions[0x1=>0x0]	1244671	1			T23	17		T24	61		T29	17
all_pins[22]	values[0x0]	3399580	1			T22	1		T23	30		T24	136
all_pins[22]	values[0x1]	2071260	1			T23	36		T24	98		T29	32
all_pins[22]	transitions[0x0=>0x1]	1244157	1			T23	24		T24	54		T29	12
all_pins[22]	transitions[0x1=>0x0]	1239513	1			T23	16		T24	60		T29	12
all_pins[23]	values[0x0]	3390515	1			T22	1		T23	37		T24	143
all_pins[23]	values[0x1]	2080325	1			T23	29		T24	91		T29	36
all_pins[23]	transitions[0x0=>0x1]	1246094	1			T23	13		T24	43		T29	21
all_pins[23]	transitions[0x1=>0x0]	1237029	1			T23	20		T24	50		T29	17
all_pins[24]	values[0x0]	3403477	1			T22	1		T23	32		T24	139
all_pins[24]	values[0x1]	2067363	1			T23	34		T24	95		T29	28
all_pins[24]	transitions[0x0=>0x1]	1235358	1			T23	17		T24	59		T29	12
all_pins[24]	transitions[0x1=>0x0]	1248320	1			T23	12		T24	55		T29	20
all_pins[25]	values[0x0]	3400564	1			T22	1		T23	35		T24	175
all_pins[25]	values[0x1]	2070276	1			T23	31		T24	59		T29	35
all_pins[25]	transitions[0x0=>0x1]	1242209	1			T23	13		T24	41		T29	22
all_pins[25]	transitions[0x1=>0x0]	1239296	1			T23	16		T24	77		T29	15
all_pins[26]	values[0x0]	3402519	1			T22	1		T23	31		T24	159
all_pins[26]	values[0x1]	2068321	1			T23	35		T24	75		T29	31
all_pins[26]	transitions[0x0=>0x1]	1239659	1			T23	16		T24	58		T29	17
all_pins[26]	transitions[0x1=>0x0]	1241614	1			T23	12		T24	42		T29	21
all_pins[27]	values[0x0]	3399452	1			T22	1		T23	31		T24	138
all_pins[27]	values[0x1]	2071388	1			T23	35		T24	96		T29	28
all_pins[27]	transitions[0x0=>0x1]	1243510	1			T23	16		T24	64		T29	17
all_pins[27]	transitions[0x1=>0x0]	1240443	1			T23	16		T24	43		T29	20
all_pins[28]	values[0x0]	3397899	1			T22	1		T23	36		T24	113
all_pins[28]	values[0x1]	2072941	1			T23	30		T24	121		T29	31
all_pins[28]	transitions[0x0=>0x1]	1242591	1			T23	17		T24	68		T29	20
all_pins[28]	transitions[0x1=>0x0]	1241038	1			T23	22		T24	43		T29	17
all_pins[29]	values[0x0]	3395950	1			T22	1		T23	35		T24	164
all_pins[29]	values[0x1]	2074890	1			T23	31		T24	70		T29	30
all_pins[29]	transitions[0x0=>0x1]	1242880	1			T23	18		T24	32		T29	13
all_pins[29]	transitions[0x1=>0x0]	1240931	1			T23	17		T24	83		T29	14
all_pins[30]	values[0x0]	3393487	1			T22	1		T23	32		T24	157
all_pins[30]	values[0x1]	2077353	1			T23	34		T24	77		T29	30
all_pins[30]	transitions[0x0=>0x1]	1242183	1			T23	15		T24	50		T29	15
all_pins[30]	transitions[0x1=>0x0]	1239720	1			T23	12		T24	43		T29	15
all_pins[31]	values[0x0]	3396557	1			T22	1		T23	26		T24	142
all_pins[31]	values[0x1]	2074283	1			T23	40		T24	92		T29	36
all_pins[31]	transitions[0x0=>0x1]	1242162	1			T23	22		T24	62		T29	19
all_pins[31]	transitions[0x1=>0x0]	1245232	1			T23	16		T24	47		T29	13