Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17709718	1			T22	425		T23	1199		T24	366
all_values[1]	17709718	1			T22	425		T23	1199		T24	366
all_values[2]	17709718	1			T22	425		T23	1199		T24	366
all_values[3]	17709718	1			T22	425		T23	1199		T24	366
all_values[4]	17709718	1			T22	425		T23	1199		T24	366
all_values[5]	17709718	1			T22	425		T23	1199		T24	366
all_values[6]	17709718	1			T22	425		T23	1199		T24	366
all_values[7]	17709718	1			T22	425		T23	1199		T24	366
all_values[8]	17709718	1			T22	425		T23	1199		T24	366
all_values[9]	17709718	1			T22	425		T23	1199		T24	366
all_values[10]	17709718	1			T22	425		T23	1199		T24	366
all_values[11]	17709718	1			T22	425		T23	1199		T24	366
all_values[12]	17709718	1			T22	425		T23	1199		T24	366
all_values[13]	17709718	1			T22	425		T23	1199		T24	366
all_values[14]	17709718	1			T22	425		T23	1199		T24	366
all_values[15]	17709718	1			T22	425		T23	1199		T24	366
all_values[16]	17709718	1			T22	425		T23	1199		T24	366
all_values[17]	17709718	1			T22	425		T23	1199		T24	366
all_values[18]	17709718	1			T22	425		T23	1199		T24	366
all_values[19]	17709718	1			T22	425		T23	1199		T24	366
all_values[20]	17709718	1			T22	425		T23	1199		T24	366
all_values[21]	17709718	1			T22	425		T23	1199		T24	366
all_values[22]	17709718	1			T22	425		T23	1199		T24	366
all_values[23]	17709718	1			T22	425		T23	1199		T24	366
all_values[24]	17709718	1			T22	425		T23	1199		T24	366
all_values[25]	17709718	1			T22	425		T23	1199		T24	366
all_values[26]	17709718	1			T22	425		T23	1199		T24	366
all_values[27]	17709718	1			T22	425		T23	1199		T24	366
all_values[28]	17709718	1			T22	425		T23	1199		T24	366
all_values[29]	17709718	1			T22	425		T23	1199		T24	366
all_values[30]	17709718	1			T22	425		T23	1199		T24	366
all_values[31]	17709718	1			T22	425		T23	1199		T24	366

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320596149

1

T22

13600

T23

38368

T24

5851

auto[1]

246114827

1

T24

5861

T1

121877

T11

30922

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121879260

1

T22

13600

T23

38368

T24

1833

auto[1]

444831716

1

T24

9879

T1

222182

T11

55947

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

560439227

1

T22

13600

T23

38368

T24

11712

auto[1]

6271749

1

T1

42365

T11

2743

T12

2851

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3070059	1			T22	425		T23	1199		T24	39
all_values[0]	auto[0]	auto[0]	auto[1]	6889439	1			T24	151		T1	35699		T11	789
all_values[0]	auto[0]	auto[1]	auto[0]	748545	1			T24	33		T1	3591		T11	85
all_values[0]	auto[0]	auto[1]	auto[1]	6804970	1			T24	143		T1	32165		T11	833
all_values[0]	auto[1]	auto[0]	auto[1]	98741	1			T1	722		T11	59		T12	47
all_values[0]	auto[1]	auto[1]	auto[1]	97964	1			T1	581		T11	35		T12	50
all_values[1]	auto[0]	auto[0]	auto[0]	3062280	1			T22	425		T23	1199		T24	63
all_values[1]	auto[0]	auto[0]	auto[1]	6843303	1			T24	148		T1	33339		T11	960
all_values[1]	auto[0]	auto[1]	auto[0]	750217	1			T24	29		T1	3741		T11	123
all_values[1]	auto[0]	auto[1]	auto[1]	6857988	1			T24	126		T1	34705		T11	658
all_values[1]	auto[1]	auto[0]	auto[1]	98189	1			T1	639		T11	60		T12	53
all_values[1]	auto[1]	auto[1]	auto[1]	97741	1			T1	685		T11	32		T12	43
all_values[2]	auto[0]	auto[0]	auto[0]	3061966	1			T22	425		T23	1199		T24	19
all_values[2]	auto[0]	auto[0]	auto[1]	6807975	1			T24	145		T1	34227		T11	877
all_values[2]	auto[0]	auto[1]	auto[0]	759492	1			T24	32		T1	3631		T11	92
all_values[2]	auto[0]	auto[1]	auto[1]	6884323	1			T24	170		T1	34007		T11	742
all_values[2]	auto[1]	auto[0]	auto[1]	98296	1			T1	625		T11	57		T12	39
all_values[2]	auto[1]	auto[1]	auto[1]	97666	1			T1	672		T11	44		T12	39
all_values[3]	auto[0]	auto[0]	auto[0]	3054701	1			T22	425		T23	1199		T24	18
all_values[3]	auto[0]	auto[0]	auto[1]	6854102	1			T24	235		T1	35348		T11	894
all_values[3]	auto[0]	auto[1]	auto[0]	749527	1			T24	23		T1	3744		T11	91
all_values[3]	auto[0]	auto[1]	auto[1]	6855797	1			T24	90		T1	32473		T11	795
all_values[3]	auto[1]	auto[0]	auto[1]	98470	1			T1	685		T11	36		T12	37
all_values[3]	auto[1]	auto[1]	auto[1]	97121	1			T1	647		T11	45		T12	48
all_values[4]	auto[0]	auto[0]	auto[0]	3071834	1			T22	425		T23	1199		T24	20
all_values[4]	auto[0]	auto[0]	auto[1]	6837403	1			T24	129		T1	34218		T11	827
all_values[4]	auto[0]	auto[1]	auto[0]	745903	1			T24	21		T1	3576		T11	94
all_values[4]	auto[0]	auto[1]	auto[1]	6858472	1			T24	196		T1	34086		T11	862
all_values[4]	auto[1]	auto[0]	auto[1]	98656	1			T1	650		T11	43		T12	59
all_values[4]	auto[1]	auto[1]	auto[1]	97450	1			T1	696		T11	44		T12	19
all_values[5]	auto[0]	auto[0]	auto[0]	3062604	1			T22	425		T23	1199		T24	20
all_values[5]	auto[0]	auto[0]	auto[1]	6844291	1			T24	193		T1	34044		T11	866
all_values[5]	auto[0]	auto[1]	auto[0]	754051	1			T24	16		T1	3594		T11	95
all_values[5]	auto[0]	auto[1]	auto[1]	6852965	1			T24	137		T1	34271		T11	845
all_values[5]	auto[1]	auto[0]	auto[1]	98491	1			T1	647		T11	42		T12	46
all_values[5]	auto[1]	auto[1]	auto[1]	97316	1			T1	679		T11	47		T12	46
all_values[6]	auto[0]	auto[0]	auto[0]	3061273	1			T22	425		T23	1199		T24	37
all_values[6]	auto[0]	auto[0]	auto[1]	6834491	1			T24	164		T1	34909		T11	706
all_values[6]	auto[0]	auto[1]	auto[0]	749393	1			T24	36		T1	3766		T11	115
all_values[6]	auto[0]	auto[1]	auto[1]	6868242	1			T24	129		T1	33393		T11	974
all_values[6]	auto[1]	auto[0]	auto[1]	97938	1			T1	656		T11	40		T12	46
all_values[6]	auto[1]	auto[1]	auto[1]	98381	1			T1	689		T11	38		T12	39
all_values[7]	auto[0]	auto[0]	auto[0]	3057885	1			T22	425		T23	1199		T24	35
all_values[7]	auto[0]	auto[0]	auto[1]	6856996	1			T24	228		T1	34843		T11	861
all_values[7]	auto[0]	auto[1]	auto[0]	742190	1			T24	15		T1	3659		T11	36
all_values[7]	auto[0]	auto[1]	auto[1]	6856503	1			T24	88		T1	33464		T11	912
all_values[7]	auto[1]	auto[0]	auto[1]	98430	1			T1	671		T11	45		T12	47
all_values[7]	auto[1]	auto[1]	auto[1]	97714	1			T1	645		T11	42		T12	50
all_values[8]	auto[0]	auto[0]	auto[0]	3057614	1			T22	425		T23	1199		T24	22
all_values[8]	auto[0]	auto[0]	auto[1]	6890374	1			T24	164		T1	34129		T11	694
all_values[8]	auto[0]	auto[1]	auto[0]	737938	1			T24	15		T1	3402		T11	118
all_values[8]	auto[0]	auto[1]	auto[1]	6827457	1			T24	165		T1	34252		T11	1002
all_values[8]	auto[1]	auto[0]	auto[1]	99172	1			T1	670		T11	41		T12	46
all_values[8]	auto[1]	auto[1]	auto[1]	97163	1			T1	679		T11	51		T12	47
all_values[9]	auto[0]	auto[0]	auto[0]	3063681	1			T22	425		T23	1199		T24	29
all_values[9]	auto[0]	auto[0]	auto[1]	6852865	1			T24	131		T1	33349		T11	903
all_values[9]	auto[0]	auto[1]	auto[0]	744927	1			T24	47		T1	3931		T11	124
all_values[9]	auto[0]	auto[1]	auto[1]	6852908	1			T24	159		T1	34062		T11	787
all_values[9]	auto[1]	auto[0]	auto[1]	98235	1			T1	623		T11	40		T12	40
all_values[9]	auto[1]	auto[1]	auto[1]	97102	1			T1	647		T11	38		T12	52
all_values[10]	auto[0]	auto[0]	auto[0]	3060158	1			T22	425		T23	1199		T24	19
all_values[10]	auto[0]	auto[0]	auto[1]	6845568	1			T24	162		T1	33975		T11	797
all_values[10]	auto[0]	auto[1]	auto[0]	742390	1			T24	6		T1	3645		T11	178
all_values[10]	auto[0]	auto[1]	auto[1]	6865371	1			T24	179		T1	34347		T11	815
all_values[10]	auto[1]	auto[0]	auto[1]	98324	1			T1	702		T11	36		T12	37
all_values[10]	auto[1]	auto[1]	auto[1]	97907	1			T1	626		T11	49		T12	48
all_values[11]	auto[0]	auto[0]	auto[0]	3066714	1			T22	425		T23	1199		T24	44
all_values[11]	auto[0]	auto[0]	auto[1]	6839461	1			T24	150		T1	34588		T11	998
all_values[11]	auto[0]	auto[1]	auto[0]	751765	1			T24	63		T1	3518		T11	90
all_values[11]	auto[0]	auto[1]	auto[1]	6855698	1			T24	109		T1	33540		T11	709
all_values[11]	auto[1]	auto[0]	auto[1]	98145	1			T1	669		T11	48		T12	45
all_values[11]	auto[1]	auto[1]	auto[1]	97935	1			T1	666		T11	34		T12	52
all_values[12]	auto[0]	auto[0]	auto[0]	3060734	1			T22	425		T23	1199		T24	31
all_values[12]	auto[0]	auto[0]	auto[1]	6856103	1			T24	177		T1	33625		T11	751
all_values[12]	auto[0]	auto[1]	auto[0]	747439	1			T24	35		T1	3657		T11	128
all_values[12]	auto[0]	auto[1]	auto[1]	6849645	1			T24	123		T1	34426		T11	893
all_values[12]	auto[1]	auto[0]	auto[1]	98726	1			T1	688		T11	38		T12	48
all_values[12]	auto[1]	auto[1]	auto[1]	97071	1			T1	637		T11	46		T12	34
all_values[13]	auto[0]	auto[0]	auto[0]	3054934	1			T22	425		T23	1199		T24	48
all_values[13]	auto[0]	auto[0]	auto[1]	6864167	1			T24	83		T1	33056		T11	827
all_values[13]	auto[0]	auto[1]	auto[0]	745952	1			T24	29		T1	3874		T11	95
all_values[13]	auto[0]	auto[1]	auto[1]	6848601	1			T24	206		T1	34680		T11	813
all_values[13]	auto[1]	auto[0]	auto[1]	98155	1			T1	637		T11	53		T12	45
all_values[13]	auto[1]	auto[1]	auto[1]	97909	1			T1	682		T11	40		T12	54
all_values[14]	auto[0]	auto[0]	auto[0]	3067663	1			T22	425		T23	1199		T24	25
all_values[14]	auto[0]	auto[0]	auto[1]	6829111	1			T24	204		T1	33802		T11	639
all_values[14]	auto[0]	auto[1]	auto[0]	759203	1			T24	23		T1	3753		T11	110
all_values[14]	auto[0]	auto[1]	auto[1]	6858126	1			T24	114		T1	34068		T11	1033
all_values[14]	auto[1]	auto[0]	auto[1]	98217	1			T1	676		T11	34		T12	43
all_values[14]	auto[1]	auto[1]	auto[1]	97398	1			T1	658		T11	48		T12	49
all_values[15]	auto[0]	auto[0]	auto[0]	3061851	1			T22	425		T23	1199		T24	16
all_values[15]	auto[0]	auto[0]	auto[1]	6850639	1			T24	125		T1	34675		T11	920
all_values[15]	auto[0]	auto[1]	auto[0]	737800	1			T24	45		T1	3533		T11	150
all_values[15]	auto[0]	auto[1]	auto[1]	6863524	1			T24	180		T1	33825		T11	674
all_values[15]	auto[1]	auto[0]	auto[1]	98577	1			T1	666		T11	46		T12	35
all_values[15]	auto[1]	auto[1]	auto[1]	97327	1			T1	697		T11	41		T12	43
all_values[16]	auto[0]	auto[0]	auto[0]	3057065	1			T22	425		T23	1199		T24	32
all_values[16]	auto[0]	auto[0]	auto[1]	6888750	1			T24	165		T1	36122		T11	718
all_values[16]	auto[0]	auto[1]	auto[0]	750553	1			T24	19		T1	3667		T11	178
all_values[16]	auto[0]	auto[1]	auto[1]	6816889	1			T24	150		T1	31908		T11	825
all_values[16]	auto[1]	auto[0]	auto[1]	98838	1			T1	667		T11	40		T12	38
all_values[16]	auto[1]	auto[1]	auto[1]	97623	1			T1	661		T11	53		T12	36
all_values[17]	auto[0]	auto[0]	auto[0]	3065207	1			T22	425		T23	1199		T24	45
all_values[17]	auto[0]	auto[0]	auto[1]	6860843	1			T24	133		T1	35051		T11	859
all_values[17]	auto[0]	auto[1]	auto[0]	761471	1			T24	29		T1	3897		T11	73
all_values[17]	auto[0]	auto[1]	auto[1]	6826533	1			T24	159		T1	32514		T11	868
all_values[17]	auto[1]	auto[0]	auto[1]	98379	1			T1	672		T11	47		T12	39
all_values[17]	auto[1]	auto[1]	auto[1]	97285	1			T1	674		T11	47		T12	50
all_values[18]	auto[0]	auto[0]	auto[0]	3055499	1			T22	425		T23	1199		T24	28
all_values[18]	auto[0]	auto[0]	auto[1]	6849142	1			T24	144		T1	35920		T11	855
all_values[18]	auto[0]	auto[1]	auto[0]	739482	1			T24	26		T1	3627		T11	138
all_values[18]	auto[0]	auto[1]	auto[1]	6869649	1			T24	168		T1	32534		T11	770
all_values[18]	auto[1]	auto[0]	auto[1]	98177	1			T1	678		T11	54		T12	40
all_values[18]	auto[1]	auto[1]	auto[1]	97769	1			T1	639		T11	39		T12	46
all_values[19]	auto[0]	auto[0]	auto[0]	3055531	1			T22	425		T23	1199		T24	18
all_values[19]	auto[0]	auto[0]	auto[1]	6858461	1			T24	150		T1	35834		T11	761
all_values[19]	auto[0]	auto[1]	auto[0]	732611	1			T24	24		T1	3768		T11	113
all_values[19]	auto[0]	auto[1]	auto[1]	6867028	1			T24	174		T1	32201		T11	975
all_values[19]	auto[1]	auto[0]	auto[1]	98816	1			T1	673		T11	39		T12	38
all_values[19]	auto[1]	auto[1]	auto[1]	97271	1			T1	642		T11	49		T12	56
all_values[20]	auto[0]	auto[0]	auto[0]	3070434	1			T22	425		T23	1199		T24	15
all_values[20]	auto[0]	auto[0]	auto[1]	6875043	1			T24	123		T1	32922		T11	1016
all_values[20]	auto[0]	auto[1]	auto[0]	745149	1			T24	19		T1	3761		T11	85
all_values[20]	auto[0]	auto[1]	auto[1]	6822613	1			T24	209		T1	35152		T11	607
all_values[20]	auto[1]	auto[0]	auto[1]	98724	1			T1	644		T11	43		T12	43
all_values[20]	auto[1]	auto[1]	auto[1]	97755	1			T1	661		T11	37		T12	46
all_values[21]	auto[0]	auto[0]	auto[0]	3060362	1			T22	425		T23	1199		T24	8
all_values[21]	auto[0]	auto[0]	auto[1]	6876631	1			T24	119		T1	34076		T11	1052
all_values[21]	auto[0]	auto[1]	auto[0]	746477	1			T24	40		T1	3653		T11	60
all_values[21]	auto[0]	auto[1]	auto[1]	6830111	1			T24	199		T1	34025		T11	689
all_values[21]	auto[1]	auto[0]	auto[1]	98589	1			T1	682		T11	51		T12	58
all_values[21]	auto[1]	auto[1]	auto[1]	97548	1			T1	650		T11	34		T12	32
all_values[22]	auto[0]	auto[0]	auto[0]	3059124	1			T22	425		T23	1199		T24	21
all_values[22]	auto[0]	auto[0]	auto[1]	6870982	1			T24	168		T1	33452		T11	833
all_values[22]	auto[0]	auto[1]	auto[0]	746356	1			T24	18		T1	3390		T11	143
all_values[22]	auto[0]	auto[1]	auto[1]	6837120	1			T24	159		T1	34970		T11	794
all_values[22]	auto[1]	auto[0]	auto[1]	98593	1			T1	674		T11	48		T12	47
all_values[22]	auto[1]	auto[1]	auto[1]	97543	1			T1	651		T11	43		T12	37
all_values[23]	auto[0]	auto[0]	auto[0]	3063487	1			T22	425		T23	1199		T24	34
all_values[23]	auto[0]	auto[0]	auto[1]	6837926	1			T24	129		T1	33257		T11	732
all_values[23]	auto[0]	auto[1]	auto[0]	749019	1			T24	38		T1	3871		T11	133
all_values[23]	auto[0]	auto[1]	auto[1]	6863534	1			T24	165		T1	34807		T11	874
all_values[23]	auto[1]	auto[0]	auto[1]	97827	1			T1	692		T11	37		T12	47
all_values[23]	auto[1]	auto[1]	auto[1]	97925	1			T1	649		T11	46		T12	39
all_values[24]	auto[0]	auto[0]	auto[0]	3058186	1			T22	425		T23	1199		T24	22
all_values[24]	auto[0]	auto[0]	auto[1]	6854419	1			T24	151		T1	34477		T11	834
all_values[24]	auto[0]	auto[1]	auto[0]	737687	1			T24	17		T1	3427		T11	98
all_values[24]	auto[0]	auto[1]	auto[1]	6863412	1			T24	176		T1	33872		T11	872
all_values[24]	auto[1]	auto[0]	auto[1]	98669	1			T1	656		T11	38		T12	44
all_values[24]	auto[1]	auto[1]	auto[1]	97345	1			T1	655		T11	29		T12	44
all_values[25]	auto[0]	auto[0]	auto[0]	3065006	1			T22	425		T23	1199		T24	39
all_values[25]	auto[0]	auto[0]	auto[1]	6886669	1			T24	183		T1	32612		T11	993
all_values[25]	auto[0]	auto[1]	auto[0]	746388	1			T24	30		T1	3742		T11	99
all_values[25]	auto[0]	auto[1]	auto[1]	6816262	1			T24	114		T1	35585		T11	649
all_values[25]	auto[1]	auto[0]	auto[1]	97759	1			T1	637		T11	40		T12	52
all_values[25]	auto[1]	auto[1]	auto[1]	97634	1			T1	687		T11	32		T12	44
all_values[26]	auto[0]	auto[0]	auto[0]	3059276	1			T22	425		T23	1199		T24	68
all_values[26]	auto[0]	auto[0]	auto[1]	6920033	1			T24	118		T1	34413		T11	875
all_values[26]	auto[0]	auto[1]	auto[0]	750141	1			T24	34		T1	3172		T11	138
all_values[26]	auto[0]	auto[1]	auto[1]	6784690	1			T24	146		T1	33114		T11	767
all_values[26]	auto[1]	auto[0]	auto[1]	97854	1			T1	645		T11	44		T12	44
all_values[26]	auto[1]	auto[1]	auto[1]	97724	1			T1	686		T11	38		T12	50
all_values[27]	auto[0]	auto[0]	auto[0]	3065545	1			T22	425		T23	1199		T24	20
all_values[27]	auto[0]	auto[0]	auto[1]	6870114	1			T24	141		T1	35101		T11	757
all_values[27]	auto[0]	auto[1]	auto[0]	754328	1			T24	23		T1	3447		T11	78
all_values[27]	auto[0]	auto[1]	auto[1]	6823667	1			T24	182		T1	33524		T11	918
all_values[27]	auto[1]	auto[0]	auto[1]	98405	1			T1	654		T11	43		T12	48
all_values[27]	auto[1]	auto[1]	auto[1]	97659	1			T1	677		T11	45		T12	37
all_values[28]	auto[0]	auto[0]	auto[0]	3058957	1			T22	425		T23	1199		T24	10
all_values[28]	auto[0]	auto[0]	auto[1]	6851999	1			T24	102		T1	35297		T11	937
all_values[28]	auto[0]	auto[1]	auto[0]	746637	1			T24	31		T1	4026		T11	105
all_values[28]	auto[0]	auto[1]	auto[1]	6856010	1			T24	223		T1	32846		T11	757
all_values[28]	auto[1]	auto[0]	auto[1]	98358	1			T1	673		T11	41		T12	47
all_values[28]	auto[1]	auto[1]	auto[1]	97757	1			T1	654		T11	46		T12	51
all_values[29]	auto[0]	auto[0]	auto[0]	3066467	1			T22	425		T23	1199		T24	45
all_values[29]	auto[0]	auto[0]	auto[1]	6850272	1			T24	175		T1	33304		T11	890
all_values[29]	auto[0]	auto[1]	auto[0]	738072	1			T24	26		T1	3631		T11	125
all_values[29]	auto[0]	auto[1]	auto[1]	6858492	1			T24	120		T1	34754		T11	798
all_values[29]	auto[1]	auto[0]	auto[1]	98214	1			T1	649		T11	39		T12	48
all_values[29]	auto[1]	auto[1]	auto[1]	98201	1			T1	632		T11	46		T12	33
all_values[30]	auto[0]	auto[0]	auto[0]	3057853	1			T22	425		T23	1199		T24	14
all_values[30]	auto[0]	auto[0]	auto[1]	6857810	1			T24	208		T1	34757		T11	915
all_values[30]	auto[0]	auto[1]	auto[0]	748648	1			T24	7		T1	4012		T11	78
all_values[30]	auto[0]	auto[1]	auto[1]	6849403	1			T24	137		T1	33092		T11	762
all_values[30]	auto[1]	auto[0]	auto[1]	98160	1			T1	654		T11	36		T12	46
all_values[30]	auto[1]	auto[1]	auto[1]	97844	1			T1	663		T11	40		T12	48
all_values[31]	auto[0]	auto[0]	auto[0]	3056206	1			T22	425		T23	1199		T24	31
all_values[31]	auto[0]	auto[0]	auto[1]	6872722	1			T24	118		T1	34796		T11	801
all_values[31]	auto[0]	auto[1]	auto[0]	749353	1			T24	49		T1	3660		T11	138
all_values[31]	auto[0]	auto[1]	auto[1]	6835860	1			T24	168		T1	33581		T11	795
all_values[31]	auto[1]	auto[0]	auto[1]	97765	1			T1	621		T11	36		T12	49
all_values[31]	auto[1]	auto[1]	auto[1]	97812	1			T1	701		T11	51		T12	48

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal