Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[1]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[2]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[3]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[4]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[5]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[6]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[7]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[8]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[9]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[10]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[11]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[12]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[13]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[14]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[15]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[16]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[17]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[18]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[19]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[20]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[21]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[22]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[23]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[24]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[25]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[26]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[27]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[28]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[29]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[30]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[31]	17346357	1			T22	713		T23	1199		T24	181

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333495604

1

T22

16153

T23

19299

T24

3025

auto[1]

221587820

1

T22

6663

T23

19069

T24

2767

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

444511169

1

T22

13717

T23

38368

T24

5792

auto[1]

110572255

1

T22

9099

T25

3613

T26

2669

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

412001457

1

T22

13788

T23

38368

T24

5792

auto[1]

143081967

1

T22

9028

T25

6890

T26

2663

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6448500	1			T22	239		T23	581		T24	101
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4690549	1			T22	63		T23	618		T24	80
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1736138	1			T22	127		T25	54		T26	34
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2225418	1			T22	126		T25	25		T26	50
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	518796	1			T25	120		T1	13789		T11	619
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1726956	1			T22	158		T25	70		T26	30
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6448654	1			T22	220		T23	532		T24	95
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4686111	1			T22	62		T23	667		T24	86
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1737534	1			T22	135		T25	48		T26	29
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2233059	1			T22	154		T25	7		T26	56
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	519183	1			T25	120		T1	13976		T11	647
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1721816	1			T22	142		T25	83		T26	44
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6442611	1			T22	192		T23	565		T24	106
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4688835	1			T22	75		T23	634		T24	75
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1737160	1			T22	142		T25	48		T26	39
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2231987	1			T22	142		T25	20		T26	34
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	517754	1			T25	179		T1	13894		T11	481
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1728010	1			T22	162		T25	67		T26	42
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6440823	1			T22	219		T23	640		T24	99
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4693302	1			T22	69		T23	559		T24	82
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1743203	1			T22	130		T25	68		T26	30
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2228026	1			T22	165		T25	19		T26	36
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	517440	1			T25	119		T1	14675		T11	480
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1723563	1			T22	130		T25	43		T26	55
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6454278	1			T22	224		T23	651		T24	98
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4686704	1			T22	71		T23	548		T24	83
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1739007	1			T22	126		T25	49		T26	35
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2228429	1			T22	134		T25	13		T26	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	518322	1			T25	130		T1	13611		T11	548
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1719617	1			T22	158		T25	42		T26	58
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6444888	1			T22	207		T23	690		T24	94
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4687817	1			T22	70		T23	509		T24	87
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1738683	1			T22	148		T25	83		T26	60
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2230370	1			T22	140		T25	21		T26	30
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	519657	1			T25	155		T1	14159		T11	478
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1724942	1			T22	148		T25	51		T26	41
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6461717	1			T22	221		T23	632		T24	90
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4677781	1			T22	74		T23	567		T24	91
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1733201	1			T22	170		T25	50		T26	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2232930	1			T22	110		T25	18		T26	38
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	517854	1			T25	114		T1	13704		T11	576
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1722874	1			T22	138		T25	71		T26	50
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6450590	1			T22	226		T23	620		T24	87
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4689529	1			T22	65		T23	579		T24	94
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1738494	1			T22	158		T25	40		T26	42
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2231088	1			T22	138		T25	30		T26	29
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	517110	1			T25	161		T1	14533		T11	449
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1719546	1			T22	126		T25	120		T26	58
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6444925	1			T22	214		T23	581		T24	96
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4687579	1			T22	70		T23	618		T24	85
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1736825	1			T22	177		T25	80		T26	50
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2235773	1			T22	116		T25	11		T26	41
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	519335	1			T25	97		T1	14391		T11	592
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1721920	1			T22	136		T25	64		T26	46
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6449055	1			T22	220		T23	499		T24	78
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4688917	1			T22	64		T23	700		T24	103
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1740207	1			T22	178		T25	70		T26	32
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2228694	1			T22	120		T25	21		T26	42
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	517339	1			T25	115		T1	13209		T11	449
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1722145	1			T22	131		T25	61		T26	49
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6457139	1			T22	237		T23	641		T24	90
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4683897	1			T22	73		T23	558		T24	91
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1736257	1			T22	123		T25	31		T26	40
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2226232	1			T22	146		T25	15		T26	42
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	515099	1			T25	148		T1	13435		T11	524
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1727733	1			T22	134		T25	55		T26	57
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6444401	1			T22	231		T23	655		T24	95
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4692004	1			T22	67		T23	544		T24	86
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1740748	1			T22	144		T25	63		T26	46
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2231480	1			T22	151		T25	4		T26	32
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	514668	1			T25	115		T1	14589		T11	449
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1723056	1			T22	120		T25	44		T26	51
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6460672	1			T22	234		T23	652		T24	105
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4681338	1			T22	56		T23	547		T24	76
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1738665	1			T22	128		T25	69		T26	59
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2228822	1			T22	174		T25	25		T26	34
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	515378	1			T25	105		T1	13430		T11	448
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1721482	1			T22	121		T25	69		T26	34
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6458263	1			T22	213		T23	545		T24	88
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4681889	1			T22	55		T23	654		T24	93
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1736923	1			T22	146		T25	42		T26	48
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2233354	1			T22	161		T25	17		T26	47
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	517706	1			T25	169		T1	13898		T11	639
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1718222	1			T22	138		T25	35		T26	32
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6447605	1			T22	211		T23	670		T24	98
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4688361	1			T22	75		T23	529		T24	83
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1734811	1			T22	104		T25	59		T26	47
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2233312	1			T22	158		T25	21		T26	46
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	521177	1			T25	158		T1	13986		T11	545
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1721091	1			T22	165		T25	45		T26	22
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6449474	1			T22	203		T23	562		T24	87
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4694206	1			T22	65		T23	637		T24	94
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1739690	1			T22	146		T25	66		T26	20
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2224042	1			T22	117		T25	16		T26	46
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	515382	1			T25	138		T1	14018		T11	686
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1723563	1			T22	182		T25	45		T26	37
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6451209	1			T22	218		T23	608		T24	78
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4685038	1			T22	73		T23	591		T24	103
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1730175	1			T22	142		T25	71		T26	53
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2240702	1			T22	138		T25	17		T26	36
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	520937	1			T25	142		T1	14141		T11	566
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1718296	1			T22	142		T25	48		T26	44
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6454829	1			T22	192		T23	606		T24	99
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4685729	1			T22	72		T23	593		T24	82
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1732469	1			T22	186		T25	59		T26	54
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2244111	1			T22	128		T25	8		T26	41
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	516150	1			T25	126		T1	13887		T11	523
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1713069	1			T22	135		T25	57		T26	38
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6454772	1			T22	211		T23	530		T24	109
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4685070	1			T22	58		T23	669		T24	72
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1735906	1			T22	116		T25	93		T26	52
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2232607	1			T22	192		T25	20		T26	34
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	517769	1			T25	106		T1	13841		T11	488
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1720233	1			T22	136		T25	52		T26	41
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6451459	1			T22	221		T23	602		T24	81
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4683758	1			T22	75		T23	597		T24	100
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1737437	1			T22	130		T25	52		T26	32
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2241960	1			T22	153		T25	15		T26	48
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	516873	1			T25	154		T1	14048		T11	579
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1714870	1			T22	134		T25	40		T26	44
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6454767	1			T22	253		T23	614		T24	109
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4686132	1			T22	75		T23	585		T24	72
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1732224	1			T22	130		T25	31		T26	35
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2235205	1			T22	145		T25	5		T26	38
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	519164	1			T25	133		T1	14008		T11	584
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1718865	1			T22	110		T25	64		T26	54
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6467606	1			T22	165		T23	559		T24	101
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4683058	1			T22	71		T23	640		T24	80
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1735716	1			T22	157		T25	62		T26	25
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2228416	1			T22	140		T25	15		T26	48
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	516121	1			T25	163		T1	14223		T11	534
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1715440	1			T22	180		T25	55		T26	52
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6458855	1			T22	248		T23	663		T24	87
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4681570	1			T22	78		T23	536		T24	94
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1728467	1			T22	136		T25	45		T26	36
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2235080	1			T22	127		T25	17		T26	35
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	517954	1			T25	115		T1	14187		T11	485
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1724431	1			T22	124		T25	51		T26	64
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6463043	1			T22	226		T23	615		T24	84
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4684011	1			T22	78		T23	584		T24	97
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1733487	1			T22	162		T25	38		T26	34
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2234518	1			T22	141		T25	35		T26	53
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	517949	1			T25	146		T1	14270		T11	588
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1713349	1			T22	106		T25	53		T26	18
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6452641	1			T22	193		T23	568		T24	88
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4689132	1			T22	63		T23	631		T24	93
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1731388	1			T22	154		T25	49		T26	51
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2236746	1			T22	137		T25	9		T26	42
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	517692	1			T25	151		T1	14122		T11	380
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1718758	1			T22	166		T25	28		T26	38
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6453136	1			T22	215		T23	630		T24	102
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4690146	1			T22	65		T23	569		T24	79
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1731952	1			T22	137		T25	35		T26	65
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2233360	1			T22	172		T25	18		T26	24
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	519445	1			T25	164		T1	13814		T11	667
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1718318	1			T22	124		T25	92		T26	36
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6455043	1			T22	210		T23	658		T24	110
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4694859	1			T22	78		T23	541		T24	71
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1734452	1			T22	162		T25	52		T26	36
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2228995	1			T22	105		T25	10		T26	40
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	517997	1			T25	148		T1	14381		T11	500
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1715011	1			T22	158		T25	89		T26	60
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6457678	1			T22	227		T23	508		T24	102
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4688979	1			T22	65		T23	691		T24	79
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1730356	1			T22	138		T25	39		T26	32
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2232382	1			T22	169		T25	18		T26	55
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	516132	1			T25	157		T1	13777		T11	486
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1720830	1			T22	114		T25	84		T26	32
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6459209	1			T22	223		T23	645		T24	108
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4682196	1			T22	60		T23	554		T24	73
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1730632	1			T22	146		T25	38		T26	51
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2234515	1			T22	126		T25	21		T26	38
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	518765	1			T25	189		T1	14102		T11	529
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1721040	1			T22	158		T25	53		T26	38
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6462112	1			T22	198		T23	580		T24	79
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4685446	1			T22	71		T23	619		T24	102
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1731702	1			T22	156		T25	40		T26	36
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2232802	1			T22	168		T25	19		T26	38
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	518028	1			T25	181		T1	14261		T11	486
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1716267	1			T22	120		T25	77		T26	25
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6469338	1			T22	241		T23	638		T24	91
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4674214	1			T22	69		T23	561		T24	90
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1725041	1			T22	147		T25	67		T26	46
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2238371	1			T22	126		T25	10		T26	21
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	519050	1			T25	113		T1	14625		T11	469
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1720343	1			T22	130		T25	23		T26	42
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6454002	1			T22	214		T23	559		T24	90
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4682252	1			T22	68		T23	640		T24	91
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1728804	1			T22	148		T25	53		T26	32
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2241770	1			T22	139		T25	16		T26	62
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	520684	1			T25	154		T1	14433		T11	484
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1718845	1			T22	144		T25	38		T26	29

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal