Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[1]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[2]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[3]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[4]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[5]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[6]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[7]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[8]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[9]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[10]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[11]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[12]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[13]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[14]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[15]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[16]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[17]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[18]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[19]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[20]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[21]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[22]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[23]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[24]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[25]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[26]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[27]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[28]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[29]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[30]	17346357	1			T22	713		T23	1199		T24	181
bins_for_gpio_bits[31]	17346357	1			T22	713		T23	1199		T24	181

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333495604

1

T22

16153

T23

19299

T24

3025

auto[1]

221587820

1

T22

6663

T23

19069

T24

2767

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333488118

1

T22

16149

T23

19299

T24

3025

auto[1]

221595306

1

T22

6667

T23

19069

T24

2767

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	10101618	1			T22	457		T23	581		T24	101
bins_for_gpio_bits[0]	auto[0]	auto[1]	308221	1			T22	35		T25	9		T26	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	308438	1			T22	35		T25	9		T26	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	6628080	1			T22	186		T23	618		T24	80
bins_for_gpio_bits[1]	auto[0]	auto[0]	10111004	1			T22	471		T23	532		T24	95
bins_for_gpio_bits[1]	auto[0]	auto[1]	308029	1			T22	38		T25	11		T26	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	308243	1			T22	38		T25	11		T26	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	6619081	1			T22	166		T23	667		T24	86
bins_for_gpio_bits[2]	auto[0]	auto[0]	10103158	1			T22	438		T23	565		T24	106
bins_for_gpio_bits[2]	auto[0]	auto[1]	308386	1			T22	38		T25	10		T26	12
bins_for_gpio_bits[2]	auto[1]	auto[0]	308600	1			T22	38		T25	10		T26	12
bins_for_gpio_bits[2]	auto[1]	auto[1]	6626213	1			T22	199		T23	634		T24	75
bins_for_gpio_bits[3]	auto[0]	auto[0]	10103601	1			T22	479		T23	640		T24	99
bins_for_gpio_bits[3]	auto[0]	auto[1]	308171	1			T22	35		T25	10		T26	12
bins_for_gpio_bits[3]	auto[1]	auto[0]	308451	1			T22	35		T25	10		T26	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	6626134	1			T22	164		T23	559		T24	82
bins_for_gpio_bits[4]	auto[0]	auto[0]	10113694	1			T22	448		T23	651		T24	98
bins_for_gpio_bits[4]	auto[0]	auto[1]	307780	1			T22	36		T25	7		T26	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	308020	1			T22	36		T25	7		T26	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	6616863	1			T22	193		T23	548		T24	83
bins_for_gpio_bits[5]	auto[0]	auto[0]	10106080	1			T22	455		T23	690		T24	94
bins_for_gpio_bits[5]	auto[0]	auto[1]	307597	1			T22	40		T25	11		T26	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	307861	1			T22	40		T25	11		T26	13
bins_for_gpio_bits[5]	auto[1]	auto[1]	6624819	1			T22	178		T23	509		T24	87
bins_for_gpio_bits[6]	auto[0]	auto[0]	10119071	1			T22	465		T23	632		T24	90
bins_for_gpio_bits[6]	auto[0]	auto[1]	308564	1			T22	36		T25	12		T26	9
bins_for_gpio_bits[6]	auto[1]	auto[0]	308777	1			T22	36		T25	12		T26	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	6609945	1			T22	176		T23	567		T24	91
bins_for_gpio_bits[7]	auto[0]	auto[0]	10112093	1			T22	484		T23	620		T24	87
bins_for_gpio_bits[7]	auto[0]	auto[1]	307879	1			T22	38		T25	7		T26	14
bins_for_gpio_bits[7]	auto[1]	auto[0]	308079	1			T22	38		T25	7		T26	14
bins_for_gpio_bits[7]	auto[1]	auto[1]	6618306	1			T22	153		T23	579		T24	94
bins_for_gpio_bits[8]	auto[0]	auto[0]	10109088	1			T22	474		T23	581		T24	96
bins_for_gpio_bits[8]	auto[0]	auto[1]	308188	1			T22	33		T25	10		T26	11
bins_for_gpio_bits[8]	auto[1]	auto[0]	308435	1			T22	33		T25	10		T26	11
bins_for_gpio_bits[8]	auto[1]	auto[1]	6620646	1			T22	173		T23	618		T24	85
bins_for_gpio_bits[9]	auto[0]	auto[0]	10109665	1			T22	485		T23	499		T24	78
bins_for_gpio_bits[9]	auto[0]	auto[1]	308065	1			T22	32		T25	12		T26	13
bins_for_gpio_bits[9]	auto[1]	auto[0]	308291	1			T22	33		T25	12		T26	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	6620336	1			T22	163		T23	700		T24	103
bins_for_gpio_bits[10]	auto[0]	auto[0]	10111138	1			T22	471		T23	641		T24	90
bins_for_gpio_bits[10]	auto[0]	auto[1]	308264	1			T22	35		T25	8		T26	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	308490	1			T22	35		T25	8		T26	14
bins_for_gpio_bits[10]	auto[1]	auto[1]	6618465	1			T22	172		T23	558		T24	91
bins_for_gpio_bits[11]	auto[0]	auto[0]	10107710	1			T22	495		T23	655		T24	95
bins_for_gpio_bits[11]	auto[0]	auto[1]	308700	1			T22	31		T25	12		T26	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	308919	1			T22	31		T25	12		T26	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	6621028	1			T22	156		T23	544		T24	86
bins_for_gpio_bits[12]	auto[0]	auto[0]	10119602	1			T22	501		T23	652		T24	105
bins_for_gpio_bits[12]	auto[0]	auto[1]	308357	1			T22	34		T25	14		T26	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	308557	1			T22	35		T25	14		T26	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	6609841	1			T22	143		T23	547		T24	76
bins_for_gpio_bits[13]	auto[0]	auto[0]	10120357	1			T22	483		T23	545		T24	88
bins_for_gpio_bits[13]	auto[0]	auto[1]	307915	1			T22	37		T25	8		T26	10
bins_for_gpio_bits[13]	auto[1]	auto[0]	308183	1			T22	37		T25	8		T26	10
bins_for_gpio_bits[13]	auto[1]	auto[1]	6609902	1			T22	156		T23	654		T24	93
bins_for_gpio_bits[14]	auto[0]	auto[0]	10107773	1			T22	436		T23	670		T24	98
bins_for_gpio_bits[14]	auto[0]	auto[1]	307710	1			T22	36		T25	12		T26	7
bins_for_gpio_bits[14]	auto[1]	auto[0]	307955	1			T22	37		T25	12		T26	7
bins_for_gpio_bits[14]	auto[1]	auto[1]	6622919	1			T22	204		T23	529		T24	83
bins_for_gpio_bits[15]	auto[0]	auto[0]	10104849	1			T22	428		T23	562		T24	87
bins_for_gpio_bits[15]	auto[0]	auto[1]	308106	1			T22	38		T25	12		T26	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	308357	1			T22	38		T25	12		T26	9
bins_for_gpio_bits[15]	auto[1]	auto[1]	6625045	1			T22	209		T23	637		T24	94
bins_for_gpio_bits[16]	auto[0]	auto[0]	10113756	1			T22	463		T23	608		T24	78
bins_for_gpio_bits[16]	auto[0]	auto[1]	308075	1			T22	35		T25	14		T26	14
bins_for_gpio_bits[16]	auto[1]	auto[0]	308330	1			T22	35		T25	14		T26	14
bins_for_gpio_bits[16]	auto[1]	auto[1]	6616196	1			T22	180		T23	591		T24	103
bins_for_gpio_bits[17]	auto[0]	auto[0]	10122448	1			T22	465		T23	606		T24	99
bins_for_gpio_bits[17]	auto[0]	auto[1]	308711	1			T22	40		T25	8		T26	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	308961	1			T22	41		T25	8		T26	12
bins_for_gpio_bits[17]	auto[1]	auto[1]	6606237	1			T22	167		T23	593		T24	82
bins_for_gpio_bits[18]	auto[0]	auto[0]	10114327	1			T22	484		T23	530		T24	109
bins_for_gpio_bits[18]	auto[0]	auto[1]	308759	1			T22	35		T25	15		T26	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	308958	1			T22	35		T25	15		T26	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	6614313	1			T22	159		T23	669		T24	72
bins_for_gpio_bits[19]	auto[0]	auto[0]	10121726	1			T22	469		T23	602		T24	81
bins_for_gpio_bits[19]	auto[0]	auto[1]	308923	1			T22	35		T25	7		T26	13
bins_for_gpio_bits[19]	auto[1]	auto[0]	309130	1			T22	35		T25	7		T26	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	6606578	1			T22	174		T23	597		T24	100
bins_for_gpio_bits[20]	auto[0]	auto[0]	10114002	1			T22	501		T23	614		T24	109
bins_for_gpio_bits[20]	auto[0]	auto[1]	307940	1			T22	27		T25	9		T26	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	308194	1			T22	27		T25	9		T26	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	6616221	1			T22	158		T23	585		T24	72
bins_for_gpio_bits[21]	auto[0]	auto[0]	10123943	1			T22	424		T23	559		T24	101
bins_for_gpio_bits[21]	auto[0]	auto[1]	307556	1			T22	38		T25	11		T26	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	307795	1			T22	38		T25	11		T26	13
bins_for_gpio_bits[21]	auto[1]	auto[1]	6607063	1			T22	213		T23	640		T24	80
bins_for_gpio_bits[22]	auto[0]	auto[0]	10112875	1			T22	484		T23	663		T24	87
bins_for_gpio_bits[22]	auto[0]	auto[1]	309321	1			T22	27		T25	6		T26	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	309527	1			T22	27		T25	6		T26	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	6614634	1			T22	175		T23	536		T24	94
bins_for_gpio_bits[23]	auto[0]	auto[0]	10123097	1			T22	499		T23	615		T24	84
bins_for_gpio_bits[23]	auto[0]	auto[1]	307716	1			T22	30		T25	7		T26	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	307951	1			T22	30		T25	7		T26	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	6607593	1			T22	154		T23	584		T24	97
bins_for_gpio_bits[24]	auto[0]	auto[0]	10112794	1			T22	443		T23	568		T24	88
bins_for_gpio_bits[24]	auto[0]	auto[1]	307748	1			T22	41		T25	8		T26	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	307981	1			T22	41		T25	8		T26	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	6617834	1			T22	188		T23	631		T24	93
bins_for_gpio_bits[25]	auto[0]	auto[0]	10110040	1			T22	483		T23	630		T24	102
bins_for_gpio_bits[25]	auto[0]	auto[1]	308174	1			T22	41		T25	11		T26	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	308408	1			T22	41		T25	11		T26	9
bins_for_gpio_bits[25]	auto[1]	auto[1]	6619735	1			T22	148		T23	569		T24	79
bins_for_gpio_bits[26]	auto[0]	auto[0]	10110092	1			T22	441		T23	658		T24	110
bins_for_gpio_bits[26]	auto[0]	auto[1]	308119	1			T22	36		T25	12		T26	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	308398	1			T22	36		T25	12		T26	12
bins_for_gpio_bits[26]	auto[1]	auto[1]	6619748	1			T22	200		T23	541		T24	71
bins_for_gpio_bits[27]	auto[0]	auto[0]	10112251	1			T22	502		T23	508		T24	102
bins_for_gpio_bits[27]	auto[0]	auto[1]	307917	1			T22	32		T25	10		T26	8
bins_for_gpio_bits[27]	auto[1]	auto[0]	308165	1			T22	32		T25	10		T26	8
bins_for_gpio_bits[27]	auto[1]	auto[1]	6618024	1			T22	147		T23	691		T24	79
bins_for_gpio_bits[28]	auto[0]	auto[0]	10116348	1			T22	452		T23	645		T24	108
bins_for_gpio_bits[28]	auto[0]	auto[1]	307783	1			T22	43		T25	7		T26	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	308008	1			T22	43		T25	7		T26	13
bins_for_gpio_bits[28]	auto[1]	auto[1]	6614218	1			T22	175		T23	554		T24	73
bins_for_gpio_bits[29]	auto[0]	auto[0]	10118245	1			T22	486		T23	580		T24	79
bins_for_gpio_bits[29]	auto[0]	auto[1]	308147	1			T22	36		T25	9		T26	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	308371	1			T22	36		T25	9		T26	10
bins_for_gpio_bits[29]	auto[1]	auto[1]	6611594	1			T22	155		T23	619		T24	102
bins_for_gpio_bits[30]	auto[0]	auto[0]	10124923	1			T22	489		T23	638		T24	91
bins_for_gpio_bits[30]	auto[0]	auto[1]	307587	1			T22	25		T25	13		T26	9
bins_for_gpio_bits[30]	auto[1]	auto[0]	307827	1			T22	25		T25	13		T26	9
bins_for_gpio_bits[30]	auto[1]	auto[1]	6606020	1			T22	174		T23	561		T24	90
bins_for_gpio_bits[31]	auto[0]	auto[0]	10115450	1			T22	464		T23	559		T24	90
bins_for_gpio_bits[31]	auto[0]	auto[1]	308892	1			T22	37		T25	10		T26	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	309126	1			T22	37		T25	10		T26	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	6612889	1			T22	175		T23	640		T24	91