Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10058239 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
190 |
| auto[1] |
7651479 |
1 |
|
|
T24 |
176 |
|
T1 |
36337 |
|
T11 |
953 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16715789 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
353 |
| auto[1] |
993929 |
1 |
|
|
T24 |
13 |
|
T1 |
4585 |
|
T11 |
30 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9990742 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
140 |
| auto[1] |
7718976 |
1 |
|
|
T24 |
226 |
|
T1 |
38598 |
|
T11 |
859 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3395319 |
1 |
|
|
T24 |
98 |
|
T1 |
17909 |
|
T11 |
398 |
| auto[1] |
auto[0] |
auto[1] |
502371 |
1 |
|
|
T24 |
5 |
|
T1 |
2459 |
|
T11 |
16 |
| auto[1] |
auto[1] |
auto[0] |
3329728 |
1 |
|
|
T24 |
115 |
|
T1 |
16104 |
|
T11 |
431 |
| auto[1] |
auto[1] |
auto[1] |
491558 |
1 |
|
|
T24 |
8 |
|
T1 |
2126 |
|
T11 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10003772 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
211 |
| auto[1] |
7705946 |
1 |
|
|
T24 |
155 |
|
T1 |
39131 |
|
T11 |
813 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16729446 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
356 |
| auto[1] |
980272 |
1 |
|
|
T24 |
10 |
|
T1 |
4599 |
|
T11 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10076595 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
215 |
| auto[1] |
7633123 |
1 |
|
|
T24 |
151 |
|
T1 |
37883 |
|
T11 |
861 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3332670 |
1 |
|
|
T24 |
90 |
|
T1 |
16734 |
|
T11 |
483 |
| auto[1] |
auto[0] |
auto[1] |
491058 |
1 |
|
|
T24 |
5 |
|
T1 |
2371 |
|
T11 |
26 |
| auto[1] |
auto[1] |
auto[0] |
3320181 |
1 |
|
|
T24 |
51 |
|
T1 |
16550 |
|
T11 |
338 |
| auto[1] |
auto[1] |
auto[1] |
489214 |
1 |
|
|
T24 |
5 |
|
T1 |
2228 |
|
T11 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10004050 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
181 |
| auto[1] |
7705668 |
1 |
|
|
T24 |
185 |
|
T1 |
38618 |
|
T11 |
1042 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16719225 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
353 |
| auto[1] |
990493 |
1 |
|
|
T24 |
13 |
|
T1 |
4865 |
|
T11 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10015783 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
152 |
| auto[1] |
7693935 |
1 |
|
|
T24 |
214 |
|
T1 |
39526 |
|
T11 |
901 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3345289 |
1 |
|
|
T24 |
96 |
|
T1 |
17188 |
|
T11 |
462 |
| auto[1] |
auto[0] |
auto[1] |
493192 |
1 |
|
|
T24 |
6 |
|
T1 |
2373 |
|
T11 |
18 |
| auto[1] |
auto[1] |
auto[0] |
3358153 |
1 |
|
|
T24 |
105 |
|
T1 |
17473 |
|
T11 |
401 |
| auto[1] |
auto[1] |
auto[1] |
497301 |
1 |
|
|
T24 |
7 |
|
T1 |
2492 |
|
T11 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10004320 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
194 |
| auto[1] |
7705398 |
1 |
|
|
T24 |
172 |
|
T1 |
37724 |
|
T11 |
833 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16720835 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
351 |
| auto[1] |
988883 |
1 |
|
|
T24 |
15 |
|
T1 |
4430 |
|
T11 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10022267 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
146 |
| auto[1] |
7687451 |
1 |
|
|
T24 |
220 |
|
T1 |
37753 |
|
T11 |
859 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3337981 |
1 |
|
|
T24 |
104 |
|
T1 |
17272 |
|
T11 |
475 |
| auto[1] |
auto[0] |
auto[1] |
491783 |
1 |
|
|
T24 |
10 |
|
T1 |
2251 |
|
T11 |
18 |
| auto[1] |
auto[1] |
auto[0] |
3360587 |
1 |
|
|
T24 |
101 |
|
T1 |
16051 |
|
T11 |
350 |
| auto[1] |
auto[1] |
auto[1] |
497100 |
1 |
|
|
T24 |
5 |
|
T1 |
2179 |
|
T11 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10015563 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
208 |
| auto[1] |
7694155 |
1 |
|
|
T24 |
158 |
|
T1 |
38720 |
|
T11 |
1067 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16719357 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
359 |
| auto[1] |
990361 |
1 |
|
|
T24 |
7 |
|
T1 |
4532 |
|
T11 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10016293 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
204 |
| auto[1] |
7693425 |
1 |
|
|
T24 |
162 |
|
T1 |
37703 |
|
T11 |
899 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3345784 |
1 |
|
|
T24 |
87 |
|
T1 |
16271 |
|
T11 |
378 |
| auto[1] |
auto[0] |
auto[1] |
493508 |
1 |
|
|
T24 |
5 |
|
T1 |
2241 |
|
T11 |
17 |
| auto[1] |
auto[1] |
auto[0] |
3357280 |
1 |
|
|
T24 |
68 |
|
T1 |
16900 |
|
T11 |
482 |
| auto[1] |
auto[1] |
auto[1] |
496853 |
1 |
|
|
T24 |
2 |
|
T1 |
2291 |
|
T11 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10017256 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
131 |
| auto[1] |
7692462 |
1 |
|
|
T24 |
235 |
|
T1 |
39236 |
|
T11 |
948 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16722930 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
356 |
| auto[1] |
986788 |
1 |
|
|
T24 |
10 |
|
T1 |
4600 |
|
T11 |
51 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10037587 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
201 |
| auto[1] |
7672131 |
1 |
|
|
T24 |
165 |
|
T1 |
38025 |
|
T11 |
1051 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3329922 |
1 |
|
|
T24 |
61 |
|
T1 |
16517 |
|
T11 |
540 |
| auto[1] |
auto[0] |
auto[1] |
490033 |
1 |
|
|
T24 |
5 |
|
T1 |
2226 |
|
T11 |
27 |
| auto[1] |
auto[1] |
auto[0] |
3355421 |
1 |
|
|
T24 |
94 |
|
T1 |
16908 |
|
T11 |
460 |
| auto[1] |
auto[1] |
auto[1] |
496755 |
1 |
|
|
T24 |
5 |
|
T1 |
2374 |
|
T11 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9994991 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
229 |
| auto[1] |
7714727 |
1 |
|
|
T24 |
137 |
|
T1 |
38479 |
|
T11 |
1191 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16726213 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
356 |
| auto[1] |
983505 |
1 |
|
|
T24 |
10 |
|
T1 |
4682 |
|
T11 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050932 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
171 |
| auto[1] |
7658786 |
1 |
|
|
T24 |
195 |
|
T1 |
37966 |
|
T11 |
780 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3319202 |
1 |
|
|
T24 |
114 |
|
T1 |
16714 |
|
T11 |
277 |
| auto[1] |
auto[0] |
auto[1] |
487348 |
1 |
|
|
T24 |
8 |
|
T1 |
2401 |
|
T11 |
12 |
| auto[1] |
auto[1] |
auto[0] |
3356079 |
1 |
|
|
T24 |
71 |
|
T1 |
16570 |
|
T11 |
470 |
| auto[1] |
auto[1] |
auto[1] |
496157 |
1 |
|
|
T24 |
2 |
|
T1 |
2281 |
|
T11 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011067 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
141 |
| auto[1] |
7698651 |
1 |
|
|
T24 |
225 |
|
T1 |
38055 |
|
T11 |
865 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16725915 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
357 |
| auto[1] |
983803 |
1 |
|
|
T24 |
9 |
|
T1 |
4390 |
|
T11 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10042050 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
217 |
| auto[1] |
7667668 |
1 |
|
|
T24 |
149 |
|
T1 |
37140 |
|
T11 |
1064 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3340438 |
1 |
|
|
T24 |
39 |
|
T1 |
16497 |
|
T11 |
605 |
| auto[1] |
auto[0] |
auto[1] |
490841 |
1 |
|
|
T24 |
1 |
|
T1 |
2207 |
|
T11 |
19 |
| auto[1] |
auto[1] |
auto[0] |
3343427 |
1 |
|
|
T24 |
101 |
|
T1 |
16253 |
|
T11 |
422 |
| auto[1] |
auto[1] |
auto[1] |
492962 |
1 |
|
|
T24 |
8 |
|
T1 |
2183 |
|
T11 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044653 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
197 |
| auto[1] |
7665065 |
1 |
|
|
T24 |
169 |
|
T1 |
36236 |
|
T11 |
1056 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16718633 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
359 |
| auto[1] |
991085 |
1 |
|
|
T24 |
7 |
|
T1 |
4496 |
|
T11 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10005441 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
210 |
| auto[1] |
7704277 |
1 |
|
|
T24 |
156 |
|
T1 |
37824 |
|
T11 |
1090 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3379272 |
1 |
|
|
T24 |
84 |
|
T1 |
18110 |
|
T11 |
463 |
| auto[1] |
auto[0] |
auto[1] |
498395 |
1 |
|
|
T24 |
7 |
|
T1 |
2479 |
|
T11 |
16 |
| auto[1] |
auto[1] |
auto[0] |
3333920 |
1 |
|
|
T24 |
65 |
|
T1 |
15218 |
|
T11 |
587 |
| auto[1] |
auto[1] |
auto[1] |
492690 |
1 |
|
|
T1 |
2017 |
|
T11 |
24 |
|
T12 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10024429 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
178 |
| auto[1] |
7685289 |
1 |
|
|
T24 |
188 |
|
T1 |
37085 |
|
T11 |
988 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16729224 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
354 |
| auto[1] |
980494 |
1 |
|
|
T24 |
12 |
|
T1 |
4447 |
|
T11 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10068481 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
155 |
| auto[1] |
7641237 |
1 |
|
|
T24 |
211 |
|
T1 |
37817 |
|
T11 |
1100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3328650 |
1 |
|
|
T24 |
96 |
|
T1 |
16214 |
|
T11 |
517 |
| auto[1] |
auto[0] |
auto[1] |
488662 |
1 |
|
|
T24 |
6 |
|
T1 |
2194 |
|
T11 |
23 |
| auto[1] |
auto[1] |
auto[0] |
3332093 |
1 |
|
|
T24 |
103 |
|
T1 |
17156 |
|
T11 |
539 |
| auto[1] |
auto[1] |
auto[1] |
491832 |
1 |
|
|
T24 |
6 |
|
T1 |
2253 |
|
T11 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10002818 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
172 |
| auto[1] |
7706900 |
1 |
|
|
T24 |
194 |
|
T1 |
36800 |
|
T11 |
947 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16718506 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
354 |
| auto[1] |
991212 |
1 |
|
|
T24 |
12 |
|
T1 |
4720 |
|
T11 |
52 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10005115 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
137 |
| auto[1] |
7704603 |
1 |
|
|
T24 |
229 |
|
T1 |
39065 |
|
T11 |
1072 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3351737 |
1 |
|
|
T24 |
95 |
|
T1 |
17968 |
|
T11 |
577 |
| auto[1] |
auto[0] |
auto[1] |
494552 |
1 |
|
|
T24 |
5 |
|
T1 |
2553 |
|
T11 |
32 |
| auto[1] |
auto[1] |
auto[0] |
3361654 |
1 |
|
|
T24 |
122 |
|
T1 |
16377 |
|
T11 |
443 |
| auto[1] |
auto[1] |
auto[1] |
496660 |
1 |
|
|
T24 |
7 |
|
T1 |
2167 |
|
T11 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10012808 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
168 |
| auto[1] |
7696910 |
1 |
|
|
T24 |
198 |
|
T1 |
36611 |
|
T11 |
1137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16724694 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
350 |
| auto[1] |
985024 |
1 |
|
|
T24 |
16 |
|
T1 |
4689 |
|
T11 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044511 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
125 |
| auto[1] |
7665207 |
1 |
|
|
T24 |
241 |
|
T1 |
38873 |
|
T11 |
917 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3328890 |
1 |
|
|
T24 |
101 |
|
T1 |
17724 |
|
T11 |
404 |
| auto[1] |
auto[0] |
auto[1] |
491622 |
1 |
|
|
T24 |
1 |
|
T1 |
2469 |
|
T11 |
10 |
| auto[1] |
auto[1] |
auto[0] |
3351293 |
1 |
|
|
T24 |
124 |
|
T1 |
16460 |
|
T11 |
482 |
| auto[1] |
auto[1] |
auto[1] |
493402 |
1 |
|
|
T24 |
15 |
|
T1 |
2220 |
|
T11 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9968237 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
164 |
| auto[1] |
7741481 |
1 |
|
|
T24 |
202 |
|
T1 |
38310 |
|
T11 |
878 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16723917 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
357 |
| auto[1] |
985801 |
1 |
|
|
T24 |
9 |
|
T1 |
4498 |
|
T11 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10042223 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
227 |
| auto[1] |
7667495 |
1 |
|
|
T24 |
139 |
|
T1 |
37997 |
|
T11 |
1043 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3333799 |
1 |
|
|
T24 |
49 |
|
T1 |
16416 |
|
T11 |
569 |
| auto[1] |
auto[0] |
auto[1] |
492069 |
1 |
|
|
T24 |
4 |
|
T1 |
2226 |
|
T11 |
28 |
| auto[1] |
auto[1] |
auto[0] |
3347895 |
1 |
|
|
T24 |
81 |
|
T1 |
17083 |
|
T11 |
428 |
| auto[1] |
auto[1] |
auto[1] |
493732 |
1 |
|
|
T24 |
5 |
|
T1 |
2272 |
|
T11 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044201 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
138 |
| auto[1] |
7665517 |
1 |
|
|
T24 |
228 |
|
T1 |
39574 |
|
T11 |
729 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16721360 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
348 |
| auto[1] |
988358 |
1 |
|
|
T24 |
18 |
|
T1 |
4781 |
|
T11 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10020771 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
110 |
| auto[1] |
7688947 |
1 |
|
|
T24 |
256 |
|
T1 |
39208 |
|
T11 |
970 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3362804 |
1 |
|
|
T24 |
94 |
|
T1 |
16849 |
|
T11 |
617 |
| auto[1] |
auto[0] |
auto[1] |
494602 |
1 |
|
|
T24 |
5 |
|
T1 |
2294 |
|
T11 |
25 |
| auto[1] |
auto[1] |
auto[0] |
3337785 |
1 |
|
|
T24 |
144 |
|
T1 |
17578 |
|
T11 |
316 |
| auto[1] |
auto[1] |
auto[1] |
493756 |
1 |
|
|
T24 |
13 |
|
T1 |
2487 |
|
T11 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10035582 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
127 |
| auto[1] |
7674136 |
1 |
|
|
T24 |
239 |
|
T1 |
38328 |
|
T11 |
783 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16724504 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
352 |
| auto[1] |
985214 |
1 |
|
|
T24 |
14 |
|
T1 |
4504 |
|
T11 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10045928 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
115 |
| auto[1] |
7663790 |
1 |
|
|
T24 |
251 |
|
T1 |
37740 |
|
T11 |
880 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3351215 |
1 |
|
|
T24 |
72 |
|
T1 |
17122 |
|
T11 |
427 |
| auto[1] |
auto[0] |
auto[1] |
494580 |
1 |
|
|
T24 |
3 |
|
T1 |
2293 |
|
T11 |
20 |
| auto[1] |
auto[1] |
auto[0] |
3327361 |
1 |
|
|
T24 |
165 |
|
T1 |
16114 |
|
T11 |
419 |
| auto[1] |
auto[1] |
auto[1] |
490634 |
1 |
|
|
T24 |
11 |
|
T1 |
2211 |
|
T11 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10028699 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
189 |
| auto[1] |
7681019 |
1 |
|
|
T24 |
177 |
|
T1 |
39011 |
|
T11 |
980 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16720878 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
354 |
| auto[1] |
988840 |
1 |
|
|
T24 |
12 |
|
T1 |
4724 |
|
T11 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10020963 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
174 |
| auto[1] |
7688755 |
1 |
|
|
T24 |
192 |
|
T1 |
38538 |
|
T11 |
1089 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3356846 |
1 |
|
|
T24 |
115 |
|
T1 |
16942 |
|
T11 |
507 |
| auto[1] |
auto[0] |
auto[1] |
494449 |
1 |
|
|
T24 |
7 |
|
T1 |
2404 |
|
T11 |
16 |
| auto[1] |
auto[1] |
auto[0] |
3343069 |
1 |
|
|
T24 |
65 |
|
T1 |
16872 |
|
T11 |
540 |
| auto[1] |
auto[1] |
auto[1] |
494391 |
1 |
|
|
T24 |
5 |
|
T1 |
2320 |
|
T11 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9999240 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
163 |
| auto[1] |
7710478 |
1 |
|
|
T24 |
203 |
|
T1 |
39327 |
|
T11 |
1053 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16718082 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
352 |
| auto[1] |
991636 |
1 |
|
|
T24 |
14 |
|
T1 |
4224 |
|
T11 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9998030 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
149 |
| auto[1] |
7711688 |
1 |
|
|
T24 |
217 |
|
T1 |
35552 |
|
T11 |
1089 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3353505 |
1 |
|
|
T24 |
83 |
|
T1 |
15616 |
|
T11 |
455 |
| auto[1] |
auto[0] |
auto[1] |
495982 |
1 |
|
|
T24 |
5 |
|
T1 |
2113 |
|
T11 |
16 |
| auto[1] |
auto[1] |
auto[0] |
3366547 |
1 |
|
|
T24 |
120 |
|
T1 |
15712 |
|
T11 |
593 |
| auto[1] |
auto[1] |
auto[1] |
495654 |
1 |
|
|
T24 |
9 |
|
T1 |
2111 |
|
T11 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011274 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
173 |
| auto[1] |
7698444 |
1 |
|
|
T24 |
193 |
|
T1 |
37954 |
|
T11 |
999 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16721688 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
356 |
| auto[1] |
988030 |
1 |
|
|
T24 |
10 |
|
T1 |
4607 |
|
T11 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10030020 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
182 |
| auto[1] |
7679698 |
1 |
|
|
T24 |
184 |
|
T1 |
38098 |
|
T11 |
974 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3345743 |
1 |
|
|
T24 |
75 |
|
T1 |
17213 |
|
T11 |
454 |
| auto[1] |
auto[0] |
auto[1] |
493899 |
1 |
|
|
T24 |
6 |
|
T1 |
2371 |
|
T11 |
20 |
| auto[1] |
auto[1] |
auto[0] |
3345925 |
1 |
|
|
T24 |
99 |
|
T1 |
16278 |
|
T11 |
475 |
| auto[1] |
auto[1] |
auto[1] |
494131 |
1 |
|
|
T24 |
4 |
|
T1 |
2236 |
|
T11 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10049434 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
222 |
| auto[1] |
7660284 |
1 |
|
|
T24 |
144 |
|
T1 |
40014 |
|
T11 |
780 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16718317 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
359 |
| auto[1] |
991401 |
1 |
|
|
T24 |
7 |
|
T1 |
4460 |
|
T11 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10001052 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
226 |
| auto[1] |
7708666 |
1 |
|
|
T24 |
140 |
|
T1 |
37305 |
|
T11 |
1006 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3382951 |
1 |
|
|
T24 |
73 |
|
T1 |
15315 |
|
T11 |
571 |
| auto[1] |
auto[0] |
auto[1] |
500159 |
1 |
|
|
T24 |
4 |
|
T1 |
2105 |
|
T11 |
14 |
| auto[1] |
auto[1] |
auto[0] |
3334314 |
1 |
|
|
T24 |
60 |
|
T1 |
17530 |
|
T11 |
402 |
| auto[1] |
auto[1] |
auto[1] |
491242 |
1 |
|
|
T24 |
3 |
|
T1 |
2355 |
|
T11 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10077163 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
186 |
| auto[1] |
7632555 |
1 |
|
|
T24 |
180 |
|
T1 |
36972 |
|
T11 |
943 |