Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10005386 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
213 |
| auto[1] |
7704332 |
1 |
|
|
T24 |
153 |
|
T1 |
38544 |
|
T11 |
987 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16724577 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
357 |
| auto[1] |
985141 |
1 |
|
|
T24 |
9 |
|
T1 |
4449 |
|
T11 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10042728 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
213 |
| auto[1] |
7666990 |
1 |
|
|
T24 |
153 |
|
T1 |
37784 |
|
T11 |
1031 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3337345 |
1 |
|
|
T24 |
93 |
|
T1 |
16887 |
|
T11 |
404 |
| auto[1] |
auto[0] |
auto[1] |
490454 |
1 |
|
|
T24 |
6 |
|
T1 |
2249 |
|
T11 |
18 |
| auto[1] |
auto[1] |
auto[0] |
3344504 |
1 |
|
|
T24 |
51 |
|
T1 |
16448 |
|
T11 |
594 |
| auto[1] |
auto[1] |
auto[1] |
494687 |
1 |
|
|
T24 |
3 |
|
T1 |
2200 |
|
T11 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |