Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9993702 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
201 |
| auto[1] |
7716016 |
1 |
|
|
T24 |
165 |
|
T1 |
37848 |
|
T11 |
1127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16720765 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
356 |
| auto[1] |
988953 |
1 |
|
|
T24 |
10 |
|
T1 |
4507 |
|
T11 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10023615 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
182 |
| auto[1] |
7686103 |
1 |
|
|
T24 |
184 |
|
T1 |
38256 |
|
T11 |
1141 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3344482 |
1 |
|
|
T24 |
127 |
|
T1 |
17279 |
|
T11 |
449 |
| auto[1] |
auto[0] |
auto[1] |
493173 |
1 |
|
|
T24 |
6 |
|
T1 |
2331 |
|
T11 |
19 |
| auto[1] |
auto[1] |
auto[0] |
3352668 |
1 |
|
|
T24 |
47 |
|
T1 |
16470 |
|
T11 |
652 |
| auto[1] |
auto[1] |
auto[1] |
495780 |
1 |
|
|
T24 |
4 |
|
T1 |
2176 |
|
T11 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |