Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10013311 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
263 |
| auto[1] |
7696407 |
1 |
|
|
T24 |
103 |
|
T1 |
37768 |
|
T11 |
990 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16721935 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
355 |
| auto[1] |
987783 |
1 |
|
|
T24 |
11 |
|
T1 |
4676 |
|
T11 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10025615 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
217 |
| auto[1] |
7684103 |
1 |
|
|
T24 |
149 |
|
T1 |
38505 |
|
T11 |
991 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3355403 |
1 |
|
|
T24 |
105 |
|
T1 |
17717 |
|
T11 |
473 |
| auto[1] |
auto[0] |
auto[1] |
495240 |
1 |
|
|
T24 |
9 |
|
T1 |
2528 |
|
T11 |
22 |
| auto[1] |
auto[1] |
auto[0] |
3340917 |
1 |
|
|
T24 |
33 |
|
T1 |
16112 |
|
T11 |
480 |
| auto[1] |
auto[1] |
auto[1] |
492543 |
1 |
|
|
T24 |
2 |
|
T1 |
2148 |
|
T11 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |