Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10047160 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
186 |
| auto[1] |
7662558 |
1 |
|
|
T24 |
180 |
|
T1 |
38333 |
|
T11 |
1171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16721119 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
350 |
| auto[1] |
988599 |
1 |
|
|
T24 |
16 |
|
T1 |
4360 |
|
T11 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10020848 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
170 |
| auto[1] |
7688870 |
1 |
|
|
T24 |
196 |
|
T1 |
36952 |
|
T11 |
1126 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3362142 |
1 |
|
|
T24 |
88 |
|
T1 |
16947 |
|
T11 |
439 |
| auto[1] |
auto[0] |
auto[1] |
494848 |
1 |
|
|
T24 |
6 |
|
T1 |
2311 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
3338129 |
1 |
|
|
T24 |
92 |
|
T1 |
15645 |
|
T11 |
651 |
| auto[1] |
auto[1] |
auto[1] |
493751 |
1 |
|
|
T24 |
10 |
|
T1 |
2049 |
|
T11 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |