Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10014781 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
160 |
| auto[1] |
7694937 |
1 |
|
|
T24 |
206 |
|
T1 |
38640 |
|
T11 |
949 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16719236 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
352 |
| auto[1] |
990482 |
1 |
|
|
T24 |
14 |
|
T1 |
4445 |
|
T11 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10007740 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
187 |
| auto[1] |
7701978 |
1 |
|
|
T24 |
179 |
|
T1 |
37119 |
|
T11 |
1012 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3351012 |
1 |
|
|
T24 |
81 |
|
T1 |
15980 |
|
T11 |
487 |
| auto[1] |
auto[0] |
auto[1] |
494875 |
1 |
|
|
T24 |
7 |
|
T1 |
2179 |
|
T11 |
26 |
| auto[1] |
auto[1] |
auto[0] |
3360484 |
1 |
|
|
T24 |
84 |
|
T1 |
16694 |
|
T11 |
476 |
| auto[1] |
auto[1] |
auto[1] |
495607 |
1 |
|
|
T24 |
7 |
|
T1 |
2266 |
|
T11 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |