Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10058239 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
190 |
| auto[1] |
7651479 |
1 |
|
|
T24 |
176 |
|
T1 |
36337 |
|
T11 |
953 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14565019 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
295 |
| auto[1] |
3144699 |
1 |
|
|
T24 |
71 |
|
T1 |
24076 |
|
T11 |
818 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10054398 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
214 |
| auto[1] |
7655320 |
1 |
|
|
T24 |
152 |
|
T1 |
38354 |
|
T11 |
1036 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2280722 |
1 |
|
|
T24 |
41 |
|
T1 |
7418 |
|
T11 |
117 |
| auto[1] |
auto[0] |
auto[1] |
1583198 |
1 |
|
|
T24 |
24 |
|
T1 |
12750 |
|
T11 |
404 |
| auto[1] |
auto[1] |
auto[0] |
2229899 |
1 |
|
|
T24 |
40 |
|
T1 |
6860 |
|
T11 |
101 |
| auto[1] |
auto[1] |
auto[1] |
1561501 |
1 |
|
|
T24 |
47 |
|
T1 |
11326 |
|
T11 |
414 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |