Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10003772 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
211 |
| auto[1] |
7705946 |
1 |
|
|
T24 |
155 |
|
T1 |
39131 |
|
T11 |
813 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14552817 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
292 |
| auto[1] |
3156901 |
1 |
|
|
T24 |
74 |
|
T1 |
23610 |
|
T11 |
774 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10022702 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
194 |
| auto[1] |
7687016 |
1 |
|
|
T24 |
172 |
|
T1 |
36529 |
|
T11 |
920 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2260618 |
1 |
|
|
T24 |
57 |
|
T1 |
6192 |
|
T11 |
96 |
| auto[1] |
auto[0] |
auto[1] |
1576866 |
1 |
|
|
T24 |
38 |
|
T1 |
10847 |
|
T11 |
475 |
| auto[1] |
auto[1] |
auto[0] |
2269497 |
1 |
|
|
T24 |
41 |
|
T1 |
6727 |
|
T11 |
50 |
| auto[1] |
auto[1] |
auto[1] |
1580035 |
1 |
|
|
T24 |
36 |
|
T1 |
12763 |
|
T11 |
299 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |