Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16719373 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
358 |
| auto[1] |
990345 |
1 |
|
|
T24 |
8 |
|
T1 |
4708 |
|
T11 |
56 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021624 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
235 |
| auto[1] |
7688094 |
1 |
|
|
T24 |
131 |
|
T1 |
38487 |
|
T11 |
1180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3381224 |
1 |
|
|
T24 |
68 |
|
T1 |
16770 |
|
T11 |
623 |
| auto[1] |
auto[0] |
auto[1] |
501831 |
1 |
|
|
T24 |
6 |
|
T1 |
2404 |
|
T11 |
26 |
| auto[1] |
auto[1] |
auto[0] |
3316525 |
1 |
|
|
T24 |
55 |
|
T1 |
17009 |
|
T11 |
501 |
| auto[1] |
auto[1] |
auto[1] |
488514 |
1 |
|
|
T24 |
2 |
|
T1 |
2304 |
|
T11 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |