Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10017256 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
131 |
| auto[1] |
7692462 |
1 |
|
|
T24 |
235 |
|
T1 |
39236 |
|
T11 |
948 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14543688 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
318 |
| auto[1] |
3166030 |
1 |
|
|
T24 |
48 |
|
T1 |
23346 |
|
T11 |
705 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10007127 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
253 |
| auto[1] |
7702591 |
1 |
|
|
T24 |
113 |
|
T1 |
36572 |
|
T11 |
924 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2279409 |
1 |
|
|
T24 |
15 |
|
T1 |
6717 |
|
T11 |
117 |
| auto[1] |
auto[0] |
auto[1] |
1588036 |
1 |
|
|
T24 |
7 |
|
T1 |
12060 |
|
T11 |
375 |
| auto[1] |
auto[1] |
auto[0] |
2257152 |
1 |
|
|
T24 |
50 |
|
T1 |
6509 |
|
T11 |
102 |
| auto[1] |
auto[1] |
auto[1] |
1577994 |
1 |
|
|
T24 |
41 |
|
T1 |
11286 |
|
T11 |
330 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |