Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011067 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
141 |
| auto[1] |
7698651 |
1 |
|
|
T24 |
225 |
|
T1 |
38055 |
|
T11 |
865 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14552315 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
272 |
| auto[1] |
3157403 |
1 |
|
|
T24 |
94 |
|
T1 |
23396 |
|
T11 |
628 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10022711 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
222 |
| auto[1] |
7687007 |
1 |
|
|
T24 |
144 |
|
T1 |
36934 |
|
T11 |
822 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2268512 |
1 |
|
|
T24 |
9 |
|
T1 |
7274 |
|
T11 |
121 |
| auto[1] |
auto[0] |
auto[1] |
1574271 |
1 |
|
|
T24 |
45 |
|
T1 |
12372 |
|
T11 |
350 |
| auto[1] |
auto[1] |
auto[0] |
2261092 |
1 |
|
|
T24 |
41 |
|
T1 |
6264 |
|
T11 |
73 |
| auto[1] |
auto[1] |
auto[1] |
1583132 |
1 |
|
|
T24 |
49 |
|
T1 |
11024 |
|
T11 |
278 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |