Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044653 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
197 |
| auto[1] |
7665065 |
1 |
|
|
T24 |
169 |
|
T1 |
36236 |
|
T11 |
1056 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14556108 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
277 |
| auto[1] |
3153610 |
1 |
|
|
T24 |
89 |
|
T1 |
24684 |
|
T11 |
685 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10039128 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
196 |
| auto[1] |
7670590 |
1 |
|
|
T24 |
170 |
|
T1 |
39044 |
|
T11 |
876 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2263445 |
1 |
|
|
T24 |
43 |
|
T1 |
7926 |
|
T11 |
121 |
| auto[1] |
auto[0] |
auto[1] |
1585018 |
1 |
|
|
T24 |
41 |
|
T1 |
13304 |
|
T11 |
348 |
| auto[1] |
auto[1] |
auto[0] |
2253535 |
1 |
|
|
T24 |
38 |
|
T1 |
6434 |
|
T11 |
70 |
| auto[1] |
auto[1] |
auto[1] |
1568592 |
1 |
|
|
T24 |
48 |
|
T1 |
11380 |
|
T11 |
337 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |