Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10024429 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
178 |
| auto[1] |
7685289 |
1 |
|
|
T24 |
188 |
|
T1 |
37085 |
|
T11 |
988 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14545589 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
284 |
| auto[1] |
3164129 |
1 |
|
|
T24 |
82 |
|
T1 |
24260 |
|
T11 |
734 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9997187 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
153 |
| auto[1] |
7712531 |
1 |
|
|
T24 |
213 |
|
T1 |
38543 |
|
T11 |
1002 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2291954 |
1 |
|
|
T24 |
65 |
|
T1 |
8031 |
|
T11 |
136 |
| auto[1] |
auto[0] |
auto[1] |
1589656 |
1 |
|
|
T24 |
46 |
|
T1 |
12909 |
|
T11 |
322 |
| auto[1] |
auto[1] |
auto[0] |
2256448 |
1 |
|
|
T24 |
66 |
|
T1 |
6252 |
|
T11 |
132 |
| auto[1] |
auto[1] |
auto[1] |
1574473 |
1 |
|
|
T24 |
36 |
|
T1 |
11351 |
|
T11 |
412 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |