Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10002818 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
172 |
| auto[1] |
7706900 |
1 |
|
|
T24 |
194 |
|
T1 |
36800 |
|
T11 |
947 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14548405 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
317 |
| auto[1] |
3161313 |
1 |
|
|
T24 |
49 |
|
T1 |
24282 |
|
T11 |
656 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10007176 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
243 |
| auto[1] |
7702542 |
1 |
|
|
T24 |
123 |
|
T1 |
38405 |
|
T11 |
818 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2283538 |
1 |
|
|
T24 |
26 |
|
T1 |
7337 |
|
T11 |
87 |
| auto[1] |
auto[0] |
auto[1] |
1586853 |
1 |
|
|
T24 |
24 |
|
T1 |
12622 |
|
T11 |
368 |
| auto[1] |
auto[1] |
auto[0] |
2257691 |
1 |
|
|
T24 |
48 |
|
T1 |
6786 |
|
T11 |
75 |
| auto[1] |
auto[1] |
auto[1] |
1574460 |
1 |
|
|
T24 |
25 |
|
T1 |
11660 |
|
T11 |
288 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |