Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044201 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
138 |
| auto[1] |
7665517 |
1 |
|
|
T24 |
228 |
|
T1 |
39574 |
|
T11 |
729 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14560535 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
277 |
| auto[1] |
3149183 |
1 |
|
|
T24 |
89 |
|
T1 |
23155 |
|
T11 |
740 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050042 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
175 |
| auto[1] |
7659676 |
1 |
|
|
T24 |
191 |
|
T1 |
36359 |
|
T11 |
970 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2262641 |
1 |
|
|
T24 |
28 |
|
T1 |
6367 |
|
T11 |
152 |
| auto[1] |
auto[0] |
auto[1] |
1576551 |
1 |
|
|
T24 |
24 |
|
T1 |
11485 |
|
T11 |
460 |
| auto[1] |
auto[1] |
auto[0] |
2247852 |
1 |
|
|
T24 |
74 |
|
T1 |
6837 |
|
T11 |
78 |
| auto[1] |
auto[1] |
auto[1] |
1572632 |
1 |
|
|
T24 |
65 |
|
T1 |
11670 |
|
T11 |
280 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |