Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10035582 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
127 |
| auto[1] |
7674136 |
1 |
|
|
T24 |
239 |
|
T1 |
38328 |
|
T11 |
783 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14572982 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
282 |
| auto[1] |
3136736 |
1 |
|
|
T24 |
84 |
|
T1 |
23984 |
|
T11 |
893 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10088134 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
151 |
| auto[1] |
7621584 |
1 |
|
|
T24 |
215 |
|
T1 |
37709 |
|
T11 |
1172 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2235450 |
1 |
|
|
T24 |
32 |
|
T1 |
6998 |
|
T11 |
149 |
| auto[1] |
auto[0] |
auto[1] |
1568208 |
1 |
|
|
T24 |
32 |
|
T1 |
12176 |
|
T11 |
551 |
| auto[1] |
auto[1] |
auto[0] |
2249398 |
1 |
|
|
T24 |
99 |
|
T1 |
6727 |
|
T11 |
130 |
| auto[1] |
auto[1] |
auto[1] |
1568528 |
1 |
|
|
T24 |
52 |
|
T1 |
11808 |
|
T11 |
342 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |