Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9999240 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
163 |
| auto[1] |
7710478 |
1 |
|
|
T24 |
203 |
|
T1 |
39327 |
|
T11 |
1053 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14558513 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
310 |
| auto[1] |
3151205 |
1 |
|
|
T24 |
56 |
|
T1 |
23625 |
|
T11 |
686 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044256 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
230 |
| auto[1] |
7665462 |
1 |
|
|
T24 |
136 |
|
T1 |
37693 |
|
T11 |
884 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2250230 |
1 |
|
|
T24 |
26 |
|
T1 |
7296 |
|
T11 |
83 |
| auto[1] |
auto[0] |
auto[1] |
1569110 |
1 |
|
|
T24 |
18 |
|
T1 |
11907 |
|
T11 |
339 |
| auto[1] |
auto[1] |
auto[0] |
2264027 |
1 |
|
|
T24 |
54 |
|
T1 |
6772 |
|
T11 |
115 |
| auto[1] |
auto[1] |
auto[1] |
1582095 |
1 |
|
|
T24 |
38 |
|
T1 |
11718 |
|
T11 |
347 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |