Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10009314 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
112 |
| auto[1] |
7700404 |
1 |
|
|
T24 |
254 |
|
T1 |
37526 |
|
T11 |
908 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16721516 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
354 |
| auto[1] |
988202 |
1 |
|
|
T24 |
12 |
|
T1 |
4491 |
|
T11 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10013101 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
150 |
| auto[1] |
7696617 |
1 |
|
|
T24 |
216 |
|
T1 |
37935 |
|
T11 |
1035 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3361232 |
1 |
|
|
T24 |
69 |
|
T1 |
17310 |
|
T11 |
512 |
| auto[1] |
auto[0] |
auto[1] |
495137 |
1 |
|
|
T24 |
5 |
|
T1 |
2383 |
|
T11 |
17 |
| auto[1] |
auto[1] |
auto[0] |
3347183 |
1 |
|
|
T24 |
135 |
|
T1 |
16134 |
|
T11 |
479 |
| auto[1] |
auto[1] |
auto[1] |
493065 |
1 |
|
|
T24 |
7 |
|
T1 |
2108 |
|
T11 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |