Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10007273 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
253 |
| auto[1] |
7702445 |
1 |
|
|
T24 |
113 |
|
T1 |
36864 |
|
T11 |
931 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16715093 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
359 |
| auto[1] |
994625 |
1 |
|
|
T24 |
7 |
|
T1 |
4687 |
|
T11 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9979927 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
232 |
| auto[1] |
7729791 |
1 |
|
|
T24 |
134 |
|
T1 |
38980 |
|
T11 |
978 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3359011 |
1 |
|
|
T24 |
73 |
|
T1 |
17838 |
|
T11 |
521 |
| auto[1] |
auto[0] |
auto[1] |
495239 |
1 |
|
|
T24 |
6 |
|
T1 |
2489 |
|
T11 |
21 |
| auto[1] |
auto[1] |
auto[0] |
3376155 |
1 |
|
|
T24 |
54 |
|
T1 |
16455 |
|
T11 |
419 |
| auto[1] |
auto[1] |
auto[1] |
499386 |
1 |
|
|
T24 |
1 |
|
T1 |
2198 |
|
T11 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |