Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10013823 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
222 |
| auto[1] |
7695895 |
1 |
|
|
T24 |
144 |
|
T1 |
37767 |
|
T11 |
880 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16728070 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
354 |
| auto[1] |
981648 |
1 |
|
|
T24 |
12 |
|
T1 |
4645 |
|
T11 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10059469 |
1 |
|
|
T22 |
425 |
|
T23 |
1199 |
|
T24 |
192 |
| auto[1] |
7650249 |
1 |
|
|
T24 |
174 |
|
T1 |
38941 |
|
T11 |
872 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3332309 |
1 |
|
|
T24 |
104 |
|
T1 |
17511 |
|
T11 |
407 |
| auto[1] |
auto[0] |
auto[1] |
490254 |
1 |
|
|
T24 |
8 |
|
T1 |
2427 |
|
T11 |
20 |
| auto[1] |
auto[1] |
auto[0] |
3336292 |
1 |
|
|
T24 |
58 |
|
T1 |
16785 |
|
T11 |
429 |
| auto[1] |
auto[1] |
auto[1] |
491394 |
1 |
|
|
T24 |
4 |
|
T1 |
2218 |
|
T11 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |